PSB4596 Siemens Semiconductor Group, PSB4596 Datasheet - Page 47
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PSB4596
Manufacturer Part Number
PSB4596
Description
Analog Line Interface Solution ALIS
Manufacturer
Siemens Semiconductor Group
Datasheet
1.PSB4596.pdf
(104 pages)
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M_VDD_OK
M_SI_1
M_SI_0
6.3.3
Default value: 7DH
CTO ms
Note: 00 means no cadence time-out programmed - no interrupt will be generated.
6.3.4
AGB
B_off
Semiconductor Group
Bit
Bit
M_Caller_ID = 0:Disable Caller_ID Interrupt
M_Caller_ID = 1:Enable Caller_ID Interrupt
M_VDD_OK = 0:Disable VDD Interrupt
M_VDD_OK = 1:Enable VDD Interrupt
M_SI_1 = 0:
M_SI_1 = 1:
M_SI_0 = 0:
M_SI_0 = 1:
AGB = 00:
AGB = 01:
AGB = 10:
AGB = 11:
XR2 Extended Register 2 (Cadence Time Out)
XR3 Extended Register 3 (DC Characteristic)
CTO 7
AGB1
7
7
Programmable Cadence Time Out:
Analog gain for analog trans-hybrid filter
Enable analog trans-hybrid filter
CTO 6
AGB0
Disable SI_1 Interrupts
Enable SI_1 Interrupts
Disable SI_0 Interrupts
Enable SI_0 Interrupts
If the time between the first two ring bursts exceeds the time
progammed in this register, a cadence interrupt is generated. The
time-out is programmable in steps of 64 ms up to 16 seconds.
Gain for analog trans-hybrid filter = 1.9 dB
Gain for analog trans-hybrid filter = 0 dB
Gain for analog trans-hybrid filter = -2.1 dB
Gain for analog trans-hybrid filter = -3.4 dB
6
6
CTO 5
B_off
5
5
DCU 1
CTO 4
4
4
47
DCU 0
CTO 3
Analog Line Interface Solution
3
3
CTO 2
DCI
2
2
PSB 4595 / PSB 4596
Programming ALIS
DCR 1
CTO 1
1
1
Data Sheet 06.98
DCR 0
CTO 0
0
0