XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 73

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for QPro Virtex-II
source-synchronous transmitter and receiver data-valid windows.
Table 68: Duty Cycle Distortion and Clock-Tree Skew
Table 69: Package Skew
Table 70: Sample Window
DS122 (v1.1) January 7, 2004
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
Duty Cycle Distortion
Clock Tree Skew
Package Skew
Sampling Error at Receiver Pins
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused
by asymmetrical rise/fall times.
T
T
in the I/O.
This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx
FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).
Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.
This parameter indicates the total sampling error of QPro Virtex-II DDR input registers across voltage, temperature, and process.
The characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
DCD_CLK0
DCD_CLK180
R
(1)
Description
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
(2)
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
(1)
Description
Description
(1)
DCD_CLK180
T
Symbol
PKGSKEW
www.xilinx.com
1-800-255-7778
T
T
DCD_CLK180
Symbol
DCD_CLK0
T
QPro Virtex-II 1.5V Military QML Platform FPGAs
Symbol
CKSKEW
T
SAMP
XQ2V6000/CF1144
Device/Package
XQ2V1000
XQ2V3000
XQ2V6000
XQ2V1000
XQ2V3000
XQ2V6000
Device
Device
All
All
Value
Value
Value
TBD
TBD
TBD
140
110
550
50
90
90
Units
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
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