XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 71

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

Output Clock Jitter
Table 63: Output Clock Jitter
Output Clock Phase Alignment
Table 64: Output Clock Phase Alignment
DS122 (v1.1) January 7, 2004
Product Specification
Notes:
1.
Notes:
1.
2.
3.
Clock Synthesis Period Jitter
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs
All CLK* outputs
Duty Cycle Precision
DLL outputs
CLKFX outputs
Values for this parameter are available at http://www.xilinx.com.
“”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
Specification also applies to PSCLK.
(1)
R
Description
Description
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_DUTY_CYCLE_DLL
CLKOUT_DUTY_CYCLE_FX
www.xilinx.com
1-800-255-7778
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
Symbol
Symbol
QPro Virtex-II 1.5V Military QML Platform FPGAs
(2)
Constraints
Constraints
Note 1
Value
Value
±140
±150
±100
±100
±150
±150
±150
±200
±150
±300
±50
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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