XQ2V3000 Xilinx, XQ2V3000 Datasheet

XQ2V3000

Manufacturer Part Number

XQ2V3000

Description

QPro Virtex-II 1.5V Military QML Platform FPGAs

Manufacturer

Xilinx

Datasheet

1.XQ2V3000.pdf (127 pages)

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DS122 (v1.1) January 7, 2004

Summary of QPro™ Virtex™-II Features

•

DS122 (v1.1) January 7, 2004

Product Specification

Industry First Military Grade Platform FPGA Solution

Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

100% Factory Tested

Guaranteed over the full military temperature range

(–55° C to +125° C)

Ceramic and Plastic Wire-Bond and Flip-Chip Grid

Array Packages

IP-Immersion Architecture

SelectRAM™ Memory Hierarchy

High-Performance Interfaces to External Memory

Arithmetic Functions

Flexible Logic Resources

High-Performance Clock Management Circuitry

Active Interconnect Technology

Densities from 1M to 6M system gates

300+ MHz internal clock speed (Advance Data)

622+ Mb/s I/O (Advance Data)

2.5 Mb of dual-port RAM in 18 Kbit block

SelectRAM resources

Up to 1 Mb of distributed SelectRAM resources

DRAM interfaces

SRAM interfaces

CAM interfaces

Dedicated 18-bit x 18-bit multiplier blocks

Fast look-ahead carry logic chains

Up to 67,584 internal registers/latches with Clock

Enable

Up to 67,584 look-up tables (LUTs) or cascadable

16-bit shift registers

Wide multiplexers and wide-input function support

Horizontal cascade chain and sum-of-products

support

Internal 3-state busing

Up to 12 DCM (Digital Clock Manager) modules

16 global clock multiplexer buffers

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

SDR/DDR SDRAM

Network FCRAM

Reduced Latency DRAM

SDR/DDR SRAM

QDR SRAM

Precise clock de-skew

Flexible frequency synthesis

High-resolution phase shifting

www.xilinx.com

1-800-255-7778

QPro Virtex-II 1.5V Military QML

Platform FPGAs

Product Specification

•

SelectIO™-Ultra Technology

Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

SRAM-Based In-System Configuration

0.15 µm 8-Layer Metal Process with 0.12 µm

High-Speed Transistors

1.5V (V

IEEE 1149.1 Compatible Boundary-Scan Logic

Support

CCAUX

Fourth generation segmented routing structure

Predictable, fast routing delay, independent of

fanout

Up to 824 user I/Os

19 single-ended and six differential standards

Programmable sink current (2 mA to 24 mA) per

I/O

Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

PCI compliant (32/33 MHz) at 3.3V

Differential Signaling

Proprietary high-performance SelectLink

Technology

Integrated VHDL and Verilog design flows

Compilation of 10M system gates designs

Internet Team Design (ITD) tool

Fast SelectMAP configuration

Triple Data Encryption Standard (DES) security

option (Bitstream Encryption)

IEEE 1532 support

Partial reconfiguration

Unlimited reprogrammability

Readback capability

CCINT

622 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

Bus LVDS I/O

Lightning Data Transport (LDT) I/O with current

driver buffers

Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

Built-in DDR input and output registers

High-bandwidth data path

Double Data Rate (DDR) link

Web-based HDL generation methodology

Auxiliary and V

) Core Power Supply, Dedicated 3.3V

CCO

I/O Power Supplies

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