LH28F800BG Sharp Electrionic Components, LH28F800BG Datasheet
LH28F800BG
Available stocks
Related parts for LH28F800BG
LH28F800BG Summary of contents
Page 1
... LH28F800BG-L (FOR SOP) DESCRIPTION The LH28F800BG-L flash memory with Smart Voltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800BG-L can operate 2.7 V and voltage operation capability realizes longer battery life and suits for cellular phone application. Its boot, ...
Page 2
... LH28F800BG +70°C (FOR SOP) 1 LH28F800BG +70°C (FOR TSOP, CSP) 1 LH28F800BGH-L –40 to +85°C (FOR TSOP, CSP) 1 Refer to the datasheet of LH28F800BG-L/BGH-L (FOR TSOP, CSP). PIN CONNECTIONS DC CHARACTERISTICS PACKAGE V deep power-down current (MAX.) CC 44-pin SOP 10 µA 48-pin TSOP (I) 10 µA ...
Page 3
... RP - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 15 32 k-WORD MAIN BLOCKS - 3 - LH28F800BG-L (FOR SOP) the byte-rewrite functionality I LOGIC CE# COMMAND WE# USER INTERFACE OE# RP# RY/BY# WRITE V STATE PP PROGRAM/ERASE MACHINE VOLTAGE SWITCH ...
Page 4
... NAME AND FUNCTION ≤ memory contents cannot be altered. Block erase and PP PPLK (see Section 6.2.3 "DC CHARACTERISTICS") produce PP to the new voltage. Do not float any power pins. With LH28F800BG-L (FOR SOP) , block erase or word HH < RP# < V produce IH HH down to GND and then CC ≤ V ...
Page 5
... To take advantage of SmartVoltage technology, allow V connection to 2 1.2 Product Overview The LH28F800BG high-performance 8 M-bit SmartVoltage flash memory organized as 512 k- word of 16 bits. The 512 k-word of data is arranged in two 4 k-word boot blocks, six 4 k-word parameter blocks and fifteen 32 k-word main blocks which are individually erasable in-system ...
Page 6
... RP# switching high until outputs are valid. Likewise, the device has a wake time (t from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared LH28F800BG-L (FOR SOP the V supply AVQV CC current CCR ...
Page 7
... VERSIONS Fig. 1 Memory Map - 7 - LH28F800BG-L (FOR SOP) Bottom Boot 32 k-Word Main Block k-Word Main Block 32 k-Word Main Block 12 32 k-Word Main Block k-Word Main Block 32 k-Word Main Block 9 32 k-Word Main Block ...
Page 8
... PRINCIPLES OF OPERATION The LH28F800BG-L SmartVoltage flash memory includes an on-chip WSM to manage block erase and word write functions. It allows for : 100% TTL- level control inputs, fixed power supplies during block erasure and word write, and minimal processor overhead with RAM-like interface timings. ...
Page 9
... PHWL ) before another The Block Erase command requires appropriate command data and an address within the block to be erased. The Word Write command requires the - 9 - LH28F800BG-L (FOR SOP) Reserved for Future Implementation Device Code Manufacture Code and the CUI ...
Page 10
... V voltages. V PPH1/2/3 CC1/2/3/4 V produce spurious results and should not be HH during attempted Refer to Table 3 for valid D 8. Don’t use the timing both OE# and WE# are LH28F800BG-L (FOR SOP) voltage ≤ read operations PP PPLK on V enables PPH1/2/3 PP ADDRESS V DQ RY/BY# PP ...
Page 11
... IH 6. Either 40H or 10H is recognized by the WSM as the word write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used LH28F800BG-L (FOR SOP) (NOTE 7) SECOND BUS CYCLE (NOTE 3) (NOTE 1) (NOTE 2) Data Oper Addr ...
Page 12
... RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked block erase error is detected, the status register should be cleared before system software attempts corrective actions LH28F800BG-L (FOR SOP) before further reads voltage ...
Page 13
... During a word write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to V However, SR.6 will remain "1" to indicate block erase suspend status LH28F800BG-L (FOR SOP the absence of PP PPH1/2/3 , SR.1 and SR.4 will IH < ...
Page 14
... RP# controls all block locking and V protection against spurious writes. Table 5 defines the write protection methods. Table 5 Write Protection Alternatives OPERATION defines WHRH1 Block Erase or Word Write - 14 - LH28F800BG-L (FOR SOP) (the same V level used for PPH1/2 (the same RP FOR COMPLETE PROTECTION ...
Page 15
... The WSM interrogates the RP# only after Block Erase or Word Write command sequences. It informs the system, depending on the attempted operation, if the RP# is not V SR.0 is reserved for future use and should be masked out when polling the status register LH28F800BG-L (FOR SOP) WWSS DPS " ...
Page 16
... Command Sequence SR. Error 0 1 Block Erase SR.5 = Error 0 Block Erase Successful Fig. 3 Automated Block Erase Flowchart LH28F800BG-L (FOR SOP) BUS COMMAND COMMENTS OPERATION Data = 20H Write Erase Setup Addr = Within Block to be Erased Erase Data = D0H Write Confirm Addr = Within Block to be Erased ...
Page 17
... SR.1 = Device Protect Error 0 1 SR.4 = Word Write Error 0 Word Write Successful Fig. 4 Automated Word Write Flowchart LH28F800BG-L (FOR SOP) BUS COMMAND COMMENTS OPERATION Setup Data = 40H or 10H Write Word Write Addr = Location to be Written Data = Data to be Written Write Word Write ...
Page 18
... Fig. 5 Block Erase Suspend/Resume Flowchart BUS COMMAND OPERATION Erase Write Suspend Read Standby Standby Erase Write Resume Read - 18 - LH28F800BG-L (FOR SOP) COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Block Erase Suspended 0 = Block Erase Completed Data = D0H Addr = X ...
Page 19
... Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write Suspend/Resume Flowchart LH28F800BG-L (FOR SOP) BUS COMMAND COMMENTS OPERATION Word Write Data = B0H Write Suspend Addr = X Status Register Data Read Addr = X Check SR ...
Page 20
... The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation System is restored. Device power-off or RP# transitions to V clear the status register LH28F800BG-L (FOR SOP power supply PP CC supply traces and PP voltage spikes and ...
Page 21
... RP# is first raised to V 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and when V is LKO PP Fig. 11, Fig. 12 and Fig.13 for more information. will inhibit LH28F800BG-L (FOR SOP) standby or sleep modes and t wake-up cycles PHQV PHWL . See Section IH ...
Page 22
... V Supply Voltage (5.0±0.5 V) CC4 CC NOTE : 1. Test condition : Ambient temperature LH28F800BG-L (FOR SOP) NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. (NOTE 1) WARNING : Stressing the device beyond the ...
Page 23
... TEST POINTS = 5.0±0.25 V (High Speed Testing Configuration) CC 2.0 TEST POINTS 0.8 (2 for a Logic "1" and V OH TTL OL (0 Output timing ends TTL 5.0±0.5 V (Standard Testing Configuration LH28F800BG-L (FOR SOP) UNIT CONDITION 0 0.0 V OUT 1.35 OUTPUT = 2 1.5 OUTPUT = 3.3±0.3 V and CC 2.0 OUTPUT 0 ...
Page 24
... UNDER TEST Includes Jig L Capacitance Fig. 10 Transient Equivalent Testing Load Circuit LH28F800BG-L (FOR SOP) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, 2 (NOTE 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed product, LH28F800BG-L85. OUT - (pF 100 ...
Page 25
... LH28F800BG-L (FOR SOP) TEST UNIT CONDITIONS MAX Max ±1 µ GND Max ±10 µ GND OUT CC CMOS Inputs 100 µ ...
Page 26
... RP write operations are not guaranteed with V ≤ V and should not be attempted RP# connection PPLK (max.) and maximum cumulative period of 80 hours. PPH1 (min.), PPH3 - 26 - LH28F800BG-L (FOR SOP) TEST UNIT CONDITIONS MAX Min ...
Page 27
... LH28F800BG-L85 NOTE MIN. 100 after the falling edge of CE# without impact on t GLQV - 27 - LH28F800BG-L (FOR SOP) (NOTE 1) LH28F800BG-L12 MAX. MIN. MAX. 150 120 150 120 150 600 600 LH28F800BG-L12 MAX ...
Page 28
... See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 10 "Transient Equivalent Testing after the falling Load Circuit" (Standard Configuration) for testing GLQV . characteristics LH28F800BG-L (FOR SOP) (NOTE 1) (NOTE 5) (NOTE 5) LH28F800BG-L85 LH28F800BG-L12 MIN. MAX. MIN. MAX. 90 120 90 120 90 120 ...
Page 29
... WE# ( DATA (D/Q) High Z (DQ - RP# ( Fig Waveform for Read Operations Device Data Valid Address Selection Address Stable t AVAV t GLQV t ELQV t GLQX t ELQX Valid Output t AVQV t PHQV - 29 - LH28F800BG-L (FOR SOP) t EHQZ t GHQZ t OH High Z ...
Page 30
... V should be held should be held word write success (SR.1/3/4 Boot Blocks, SR.3/4 Parameter Blocks and Main Blocks). for block erase LH28F800BG-L (FOR SOP) LH28F800BG-L12 UNIT MAX. MIN. MAX. 150 ns 1 µ 100 ...
Page 31
... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 9 "Transient Input/Output Reference for block erase or Waveform" and Fig. 10 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F800BG-L (FOR SOP) (NOTE 1) (NOTE 6) (NOTE 6) LH28F800BG-L85 LH28F800BG-L12 MIN. MAX. MIN. MAX. ...
Page 32
... Write Read Array command. Fig Waveform for WE#-Controlled Write Operations (NOTE 3) (NOTE 4) (NOTE WHAX AVAV AVWH t WHEH t WHGL t t WHWL WHQV1/2/3/4 t WLWH t DVWH t WHDX WHRL t PHHWH t VPWH - 32 - LH28F800BG-L (FOR SOP) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
Page 33
... V should be held should be held word write success (SR.1/3/4 Boot Blocks, SR.3/4 Parameter Blocks and Main Blocks). for block erase LH28F800BG-L (FOR SOP) LH28F800BG-L12 UNIT MAX. MIN. MAX. 150 ns 1 µ 100 ...
Page 34
... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 9 "Transient Input/Output Reference for block erase or Waveform" and Fig. 10 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F800BG-L (FOR SOP) (NOTE 1) (NOTE 6) (NOTE 6) LH28F800BG-L85 LH28F800BG-L12 MIN. MAX. MIN. MAX. ...
Page 35
... Write Read Array command. Fig Waveform for CE#-Controlled Write Operations (NOTE 3) (NOTE 4) (NOTE AVAV AVEH EHAX t EHWH t EHGL t t EHEL EHQV1/2/3/4 t ELEH t DVEH t EHDX EHRL t PHHEH t VPEH - 35 - LH28F800BG-L (FOR SOP) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
Page 36
... A reset time RP# going high until outputs are valid. 4. When the device power-up, holding RP#-low minimum 100 ns is required after V range and also has been in stable there LH28F800BG-L (FOR SOP 3.3±0 5.0±0 MIN. MAX. MIN. ...
Page 37
... PP PP (NOTE 1) MIN. TYP. MAX. MIN. TYP 1.44 2 0.19 2 1. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested LH28F800BG-L (FOR SOP) (NOTE 12.0±0 (NOTE 1) (NOTE 1) MAX. MIN. TYP. MAX. 17.7 12.6 26.1 24.5 0.58 0.42 0.11 0.11 0.61 0.51 0.32 0. ...
Page 38
... Excludes system-level overhead +70˚ NOTE MIN. TYP These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested LH28F800BG-L (FOR SOP) (NOTE 5.0±0 12.0±0 (NOTE 1) (NOTE 1) MAX. MIN. TYP. MAX. 12.2 8.4 18.3 17 0.4 0.28 0.08 ...
Page 39
... N = 44-pin SOP (SOP044-P-0600) VALID OPERATIONAL COMBINATIONS = 2 3.3±0 load load, 1.5 V I/O Levels 120 ns 100 ns 150 ns 130 LH28F800BG-L (FOR SOP) 100 ns (3.3 0.3 V), 120 ns (2.7 to 3.6 V) 150 ns (2 5.0±0 5.0±0. 100 pF load load, TTL I/O Levels 1.5 V I/O Levels 90 ns ...
Page 40
SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...