PEB3086 Infineon Technologies, PEB3086 Datasheet - Page 136

• Manufacturer Part Number: PEB3086
• Description: ISDN Subscriber Access Controller
• Manufacturer: Infineon Technologies

like registers are indicated by an “x” (stands for “D” and “B”) to indicate it is relevant for
D- and B-channel (e.g. ISTAx means ISTAD/ISTAB).
3.8.2
The HDLC controllers can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a D-channel two-byte address (LAPD) is shown below:
For address recognition on the D-channel the ISAC-SX contains four programmable
registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values
for the “group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
The structure of a B-channel two-byte address is as follows:
For address recognition on the B-channel the ISAC-SX contains four programmable
registers for individual Receive Address High and Low values (RAH1, 2 and RAL1, 2),
plus two fixed values for the High Address Byte (Group Address = ’FE’ or ’FC’) and one
fixed value for the Low Address Byte (Group Address = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
Operating Modes
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEx registers:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
Data Sheet
RAH1, 2, Group Address C/R 0
SAPI1, 2, SAPG
High Address Byte
High Address Byte
Message Transfer Modes
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
C/R 0
136
RAL1, 2, Group Address
TEI 1, 2, TEIG
Low Address Byte
Low Address Byte
Description of Functional Blocks
EA
PEB 3086
2003-01-30
ISAC-SX