SAB80C517A-N18 Siemens Semiconductor Group, SAB80C517A-N18 Datasheet - Page 52

• Manufacturer Part Number: SAB80C517A-N18
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: Siemens Semiconductor Group

Power Down Mode
Power Down Mode
The power down mode is entered by two consecutive instructions directly following each other.
The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.
automatically be cleared after having been set.
The instruction that sets bit PDS is the last instruction executed before going into power down
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.
mode. The only exit from power down mode is a hardware reset.
The status of all output lines of the controller can be looked up in table 8.
The status of all output lines of the controller can be looked up in table 8.
Hardware Controlled Power Down Mode
Hardware Controlled Power Down Mode
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware
Power Down Mode; this is independent of the state of pin PE/SWD.
Power Down Mode; this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
same time the port pins and several control lines enter a floating state as shown in table 8. In
same time the port pins and several control lines enter a floating state as shown in table 8. In
this state the power consumption is reduced to the power down current IPD. Also the supply
this state the power consumption is reduced to the power down current IPD. Also the supply
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
Hardware Power Down Mode without affecting the low power consumption.
Hardware Power Down Mode without affecting the low power consumption.
Termination of HWPD Mode:
Termination of HWPD Mode:
This power down state is maintained while pin HWPD is held active. If HWPD goes to high
This power down state is maintained while pin HWPD is held active. If HWPD goes to high
level (inactive state) an automatic start up procedure is performed:
level (inactive state) an automatic start up procedure is performed:
– First the pins leave their floating condition and enter their default reset state
– First the pins leave their floating condition and enter their default reset state
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
– Because the oscillator watchdog is active it detects a failure condition if the
– Because the oscillator watchdog is active it detects a failure condition if the
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active
– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active
Semiconductor Group
(as they had immediately before going to float state).
(as they had immediately before going to float state).
oscillator starts up very fast (typ. less than 2 microseconds).
oscillator starts up very fast (typ. less than 2 microseconds)
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
and supplies the internal clock from the RC oscillator.
and supplies the internal clock from the RC oscillator.
the part from reset with oscillator watchdog status flag not set.
the part from reset with oscillator watchdog status flag not set
When automatic start of the watchdog was enabled (PE/SWD connected to V
When automatic start of the watchdog was enabled (PE/SWD connected to V
the Watchdog Timer will start, too (with its default reload value for time-out period).
the Watchdog Timer will start, too (with its default reload value for time-out period).
during Hardware Power Down it is terminated and the device performs the normal
during Hardware Power Down it is terminated and the device performs the normal
reset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).
reset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).
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SAB 80C517A/83C517A-5
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1994-05-01
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