SAB80C517A-N18 Siemens Semiconductor Group, SAB80C517A-N18 Datasheet - Page 39

• Manufacturer Part Number: SAB80C517A-N18
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: Siemens Semiconductor Group

Semiconductor Group
Compare
In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 register or the compare timer register. If the count value in the
timer registers matches one of the stored value, an appropriate output signal is generated at
the corresponding pin(s) and an interrupt is requested. Three compare modes are provided:
Mode 0:
Mode 1:
Mode 2:
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to 'freeze' the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0:
Mode 1:
It returns to low level at timer overflow.
A timer overflow signal does not affect the compare-output.
as follows (see figure 9)
– When a compare match occurs with register COMSET, a high level
– When a compare match occurs in register COMCLR, a low level
port 1 pins CC0 to CC3.
causes the timer 2 contents to be latched into this register.
Upon a match the output signal changes from low to high.
The transition of the output signal can be determined by software.
In compare mode 2 the concurrent compare output pins on Port 5 are used
Capture is performed in response to a transition at the corresponding
Write operation into the low-order byte of the dedicated capture register
appears at the pins of port 5 whose corresponding bits in the mask
register SETMSK (address 0A5
appears at the pins of port 5 whose corresponding bits in the mask
register CLRMSK (address 0A6
Additionally the Port 5 pins used for compare mode 2 may also be
directly written to by write instructions to SFR P5. Of course, the pins
can also be read under program control.
38
H
H
) are set.
) are set.
SAB 80C517A/83C517A-5
1994-05-01