XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet - Page 29

• Manufacturer Part Number: XR16C2850IJ
• Description: 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
• Manufacturer: EXAR [Exar Corporation]

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REV. 2.1.3
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
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LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, LOW, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
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LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control enabled by
EFR bit-6. The RTS# output must be asserted before the auto RTS can take effect. If the modem interface is
not used, this output may be used as a general purpose output.
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MCR[2]: Reserved
OP1# is not available as an output pin on the 2850. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
4.7
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW. If auto RTS flow control is enabled, it will take effect after this bit has
been set.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
LCR B
X
0
0
1
1
IT
-5
LCR B
X
0
1
0
1
IT
T
-4
ABLE
11: P
LCR B
ARITY SELECTION
29
0
1
1
1
1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
IT
-3
Forced parity to space, “0”
Force parity to mark, “1”
P
ARITY SELECTION
Even parity
Odd parity
No parity
XR16C2850