XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet - Page 23

• Manufacturer Part Number: XR16C2850IJ
• Description: 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 2.1.3
SEE”RECEIVER” ON PAGE 14.
SEE”TRANSMITTER” ON PAGE 12.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
DREV
XON1 RD/WR
XON2 RD/WR
FCTR RD/WR
N
DVID
TRG
R
EFR
FC
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
W
R
WR
RD
RD
RD
EAD
RITE
/
Enable
RX/TX
Mode
B
Bit-7
Bit-7
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
SCPAD
Enable
Swap
B
Bit-6
Bit-6
Bit-6
Auto
RTS
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
-6
Enhanced Registers
Special
Select
Table
B
Char
Bit-5
Bit-5
Bit-5
Bit-1
Bit-5
Bit-5
Bit-5
Bit-5
Trig
IT
0
-5
23
FCR[5:4],
IER [7:4],
ISR [5:4],
MCR[7:5]
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Enable
B
Table
Bit-4
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Bit-4
Bit-4
Trig
IT
1
-4
S
HADED BITS ARE ENABLED WHEN
Direction
Control
RS485
B
ware
Bit-3
Bit-3
Bit-3
Auto
Soft-
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
0
-3
RX IR
B
Input
ware
Bit-2
Bit-2
Bit-2
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
Inv.
IT
0
-2
B
Bit-1
Bit-1
Bit-1
Auto
Bit-1
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
RTS
Hyst
Cntl
IT
1
-1
EFR B
B
ware
Flow
Bit-0
Bit-0
Bit-0
Auto
RTS
Hyst
Bit-0
Soft-
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
IT
0
-0
IT
XR16C2850
-4=1
LCR ≠ 0xBF
DLM=0x00
LCR=0
LCR[7] = 1
DLL=0x00
C
OMMENT
X
BF