XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet - Page 13

• Manufacturer Part Number: XR16C2850IJ
• Description: 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 2.1.3
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
F
2.10.3
IGURE
IGURE
7. T
8. T
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
16X or 8X
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
(Xoff1/2 and Xon1/2 Reg.
Clock
Flow Control Characters
16X or 8X
Data
Byte
O
O
Clock
PERATION IN NON
PERATION IN
Transmit Shift Register (TSR)
Data Byte
Transmit
FIFO
Transmit
Register
Holding
(THR)
-FIFO M
AND
Transm it Data Shift Register
F
LOW
ODE
Transmit
FIFO
(TSR)
13
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
THR Interrupt (ISR bit-1) falls
below the programm ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1
ODE
M
S
B
T XF IF O 1
TXNOFIFO1
L
S
B
XR16C2850