XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet - Page 12

• Manufacturer Part Number: XR16C2850IJ
• Description: 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see CLK8/16 pin description). The transmitter sends the start-bit
followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status
of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
O
2.10
2.10.1
2.10.2
UTPUT
MCR Bit-7=1
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with CLK8/16 pin = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with CLK8/16 pin = 0
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
T
ABLE
O
UTPUT
5: T
MCR Bit-7=0
(D
153.6k
230.4k
460.8k
921.6k
EFAULT
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
400
Data Rate
)
Clock (Decimal)
D
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
16x
14.7456 MH
D
12
IVISOR FOR
Clock (HEX)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
V
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
xr
D
E
REV. 2.1.3
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)