MC9S08GT16 MOTOROLA [Motorola, Inc], MC9S08GT16 Datasheet - Page 94

• Manufacturer Part Number: MC9S08GT16
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Chapter 6 Parallel Input/Output
PTGDn — Port PTG Data Register Bit n (n = 0–7)
PTGPEn — Pullup Enable for Port G Bit n (n = 0–7)
PTGSEn — Slew Rate Control Enable for Port G Bit n (n = 0–7)
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For port G pins that are inputs, reads return the logic level on the pin. For port G pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port G pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
For port G pins that are outputs, these read/write control bits determine whether the slew rate
controlled outputs are enabled. For port G pins that are configured as inputs, these bits are ignored.
PTGD
PTGPE
PTGSE
PTGDD
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
PTGPE7
PTGSE7
PTGD7
Bit 7
0
0
0
0
PTGPE6
PTGSE6
MC9S08GB/GT Data Sheet, Rev. 2.3
PTGD6
Figure 6-15. Port G Registers
6
0
0
0
0
PTGPE5
PTGSE5
PTGD5
5
0
0
0
0
PTGPE4
PTGSE4
PTGD4
4
0
0
0
0
PTGPE3
PTGSE3
PTGD3
3
0
0
0
0
PTGPE2
PTGSE2
PTGD2
2
0
0
0
0
PTGPE1
PTGSE1
PTGD1
Freescale Semiconductor
1
0
0
0
0
PTGPE0
PTGSE0
PTGD0
Bit 0
0
0
0
0