CY14B104N CYPRESS [Cypress Semiconductor], CY14B104N Datasheet - Page 13

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CY14B104N

Manufacturer Part Number
CY14B104N
Description
4 Mbit (512K x 8/256K x 16) nvSRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.
Switching Waveforms
Notes
Document #: 001-07102 Rev. *L
t
t
t
t
t
t
25. The software sequence is clocked with CE controlled or OE controlled reads.
26. The six consecutive addresses must be read in the order listed in
RC
SA
CW
HA
RECALL
SS
Parameters
cycle, no further read or write operation must be performed for t
[27, 28]
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
Description
Figure 13. Autostore Enable / Disable Cycle
SS
Table 1
duration. If these conditions are not met, the software sequence is aborted.
on page 5. WE must be HIGH during all six consecutive cycles. After the sixth address read
Min
20
15
0
0
20 ns
Max
200
100
Min
25
20
0
0
25 ns
CY14B104L, CY14B104N
[25, 26]
Max
200
100
[26]
Min
45
30
0
0
45 ns
Max
200
100
Page 13 of 25
Unit
ns
ns
μs
μs
ns
ns
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