Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 72

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Whether address translation (Figure 26) takes place depends on the type
of CPU cycle as follows.
•
•
Figure 26.
•
MMU Registers
Three MMU registers are used to program a specific configuration of
logical and physical memory.
Memory Cycles
Address Translation occurs for all memory access cycles including
instruction and operand fetches, memory data reads and writes,
hardware interrupt vector fetch, and software interrupt restarts.
I/O Cycles
The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O
address space corresponds directly with the 16-bit physical I/O
address space. The four high-order bits (A16–A19) of the physical
address are always
DMA Cycles
When the Z8X180 on-chip DMAC is using the external bus, the
MMU is physically bypassed. The 20-bit source and destination
registers in the DMAC are directly output on the physical address bus
(A0–A19).
“ 0000”
PA19
I/O Address Translation
PA16 PA15
0
during I/O cycles.
LA15
M PU Us e r M anual
UM005001-ZMP0400
PA0
LA0
Z 8018x Fam il y
Logical Address
Physical Address
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