Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 314

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

298
UM005001-ZMP0400
Register
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address
Register Channel 0L:
DMA Destination Address
Register Channel 0H:
DMA Destination Address
Register Channel 0B:
DMA Byte Count Register
Channel 0L:
DMA Byte Count Register
Channel 0H:
DMA Memory Address
Register
Channel 1L:
DMA Memory Address
Register
Channel 1H:
Z8018x Family
MPU User Manual
Table 57. Internal I/O Registers (Continued)
TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
SAR0L
SAR0H
SAR0B
DAR0L
DAR0H
DAR0B
BCROL
BCROH
MAR1L
MAR1H
Mnemonics Address
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
9
6
4
5
7
8
0
1
2
3
4
5
7
8
6
Read only
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
Bits 0-2 (3) are used for SAR0B
Bits 0-2 (3) are used for DAR0B
A
A
X
X
X
X
19
X
X
X
X
19
*,
*,
A
X
X
X
X
A
X
X
X
X
18
18
,
,
A
A
0
0
1
1
17
0
0
1
1
17
,
,
A
A
0
1
0
1
0
1
0
1
16
16
Remarks
DMA Transfer Request
DMA Transfer Request
RDR0 (ASCI0)
Not used
DREQ
RDR1 (ASCI1)
DREQ
TDR0 (ASCI0)
Not used
TDR1 (ASCI1)
0
0
(external)
(external)