Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 32

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

IORQ
WR
Phi
RD
IORQ
Figure 7.
When IOC is
required by the Z80 family of peripherals. The IORQ and RD signals go
active as a result of the rising edge of T2. This timing allows the Z8X180
to satisfy the setup times required by the Z80 peripherals on those two
signals (Figure ).
Figure 8.
For the remainder of this document, assume that M1E is
WR
Phi
RD
T1
I/O Read and Write Cycles with IOC = 1 Timing Diagram
I/O Read and Write cycles with IOC = 0 Timing Diagram
0
T1
, the timing of the IORQ and RD signals match the timing
T2
T2
TW
TW
T3
T3
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
0
and IOC is
0
.
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