CY8C20110_0809 CYPRESS [Cypress Semiconductor], CY8C20110_0809 Datasheet

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CY8C20110_0809

Manufacturer Part Number
CY8C20110_0809
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Features
Cypress Semiconductor Corporation
Document Number: 001-17345 Rev. *E
10 configurable IOs supporting
2.4V to 3.6V and 4.75V to 5.25V operating voltage
Industrial temperature range: –40°C to +85°C
I
Reduce BOM cost
Low operating current
Available in 16-pin COL and 16-pin SOIC packages
2
C slave interface for configuration and communication
CapSense
LED drive
All GPIOs support LED dimming with configurable delay op-
tion
Interrupt outputs.
WAKE on interrupt input
Bi-directional sleep control pin
User defined input or output
I2C data transfer rate up to 400 kbps
Internal oscillator - no external oscillators or crystal
Free development tool - no external tuning components
Active current: continuous sensor scan: 1.5 mA
Deep sleep current: 4 uA
TM
buttons
198 Champion Court
CapSense
Overview
The CapSense Express
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions.
The CY8C20110 is optimized for dimming LEDs in 15 selectable
duty cycles for back light applications. The device can be
configured to have up to 10 GPIOs connected to the PWM
output. The PWM duty cycle is programmable for variable LED
intensities.
The user has the ability to configure buttons, outputs, and param-
eters through specific commands sent to the I
have the flexibility of mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive, and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20110.
The user is able to configure registers with parameters needed
to adjust the operation and sensitivity of the CapSense system.
CY8C20110 supports a standard I
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, along with sleep and watchdog timers.
System resources provide additional capability, such as a config-
urable I
resets. The Analog system contains the CapSense PSoC block
which supports capacitive sensing of up to 10 inputs.
2
C slave communication interface and various system
San Jose
Express™-10 Configurable
GPIOs with PWM Control
,
CA 95134-1709
TM
controller allows the control of 10 IOs
Revised September 06, 2008
2
C serial communication
CY8C20110
• 408-943-2600
2
C port. The IOs
[+] Feedback

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CY8C20110_0809 Summary of contents

Page 1

Features ■ 10 configurable IOs supporting ❐ CapSense TM buttons ❐ LED drive ❐ All GPIOs support LED dimming with configurable delay op- tion ❐ Interrupt outputs. ❐ WAKE on interrupt input ❐ Bi-directional sleep control pin ❐ User defined ...

Page 2

Logic Block Diagram CapSense Express CapSense Document Number: 001-17345 Rev. *E External 10 Configurable IOs with Vcc PWM Control 2.4 - 5.25V TM Core SYSTEM BUS 2KB Flash 512B Configuration and SRAM Control Engine Interrupt Controller Clock Sources (Internal Main ...

Page 3

Pinouts Table 1. Pin Definitions - 16 Pin COL Pin Number Name 1 GP0[0] 2 GP0[ SCL SDA 5 GP1[0] 6 GP1[1] 7 VSS 8 GP1[2] 9 GP1[3] 10 GP1[4] 11 XRES ...

Page 4

GP0[3] GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0] Table 2. Pin Definitions - 16 Pin SOIC Pin Number Name 1 GP0[3] 2 CSInt 3 GP0[4] 4 GP0[0] 5 GP0[ SCL SDA 8 GP1[0] ...

Page 5

The CapSense Analog System The CapSense analog system contains the capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. Additional System Resources ...

Page 6

Figure 3. LED Dimming Mode 1: Change Intensity on ON/OFF Button Status Document Number: 001-17345 Rev. *E CY8C20110 Page [+] Feedback ...

Page 7

Figure 4. LED Dimming Mode 2: Flash Intensity on ON Button Status Figure 5. LED Dimming Mode 3: Hold Intensity After ON→OFF Button Transition Document Number: 001-17345 Rev. *E CY8C20110 Page [+] Feedback ...

Page 8

Figure 6. LED Dimming Mode 4: Toggle Intensity on ON→OFF or OFF→ON Button Transitions Modes of Operation CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: ■ Active Mode ...

Page 9

Electrical Specifications Absolute Maximum Ratings Parameter Description T Storage temperature STG T Ambient temperature with power A applied V Supply voltage on V relative input voltage voltage applied to tri-state IOZ ...

Page 10

DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C <TA< 85°C, 3.0V to 3.6V and -40°C<TA< 85°C respectively. Typical parameters apply to ...

Page 11

DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C<TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. These are for design guidance only. ...

Page 12

DC POR and LVD Specifications Parameter Description V Value/ PPOR Trip for 2.7V PPOR0 3.3V, 5V PPOR1 DD V Value for LVD trip DD VLVD0 V = 2.7V DD VLVD2 V = ...

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Capsense Electrical Characteristics Max (V) Typical (V) 5.25 5.0 3.6 3.3 3.02 2.7 AC Electrical Characteristics 5V and 3.3V AC General Purpose IO Specifications Parameter Description TRise0 Rise time, strong mode, Cload = 50pF, Port 0 TRise1 Rise time, strong ...

Page 14

AC I2C Specifications Parameter Description F SCL clock frequency SCLI2C T Hold time (repeated) START HDSTAI2C condition. After this period, the first clock pulse is generated. T LOW period of the SCL clock LOWI2C T HIGH period of the SCL ...

Page 15

Ordering Information Ordering Code CY8C20110-LDX2I CY8C20110-SX2I Thermal Impedances by Package Package [9] 16 COL 16 SOIC Solder Reflow Peak Temperature Package [9] 16 COL 16 SOIC Notes + Power x θ JA. 8. Higher ...

Page 16

Package Diagram Figure 8. 16L Chip On Lead Package Outline (SAWN) - 001-09116 – (Pb-Free) Document Number: 001-17345 Rev. *E Figure 9. 16-Pin (150-Mil) SOIC (51-85068) CY8C20110 001-09116 *D 51-85068-*B Page [+] Feedback ...

Page 17

Document History Page Document Title: CY8C20110 CapSense Express™-10 Configurable GPIOs with PWM Control Document Number: 001-17345 Orig. of REV. ECN. Change ** 1341766 TUP/SFV *A 1494145 TUP/AESA *B 1773608 TUP/AESA *C 2091026 DZU/MOHD /AESA *D 2404731 DZU/MOHD /PYRS *E 2549237 ...

Page 18

Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless ...

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