PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 33
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PCA8534AH-Q900
Manufacturer Part Number
PCA8534AH-Q900
Description
Universal LCD driver for low multiplex rates
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCA8534AH-Q900.pdf
(44 pages)
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NXP Semiconductors
PCA8534A_2
Product data sheet
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA8534A. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCA8534A with
different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA8534A asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA8534A to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA8534A are shown in
Fig 22. Cascaded PCA8534A configuration
V
V
V
SS
DD
CONTROLLER
PROCESSOR/
LCD
MICRO-
MICRO-
HOST
R
≤
All information provided in this document is subject to legal disclaimers.
2C
t
r
b
Rev. 02 — 1 June 2010
SYNC
OSC
SYNC
SDA
CLK
SCL
SDA
SCL
CLK
OSC
A0
Universal LCD driver for low multiplex rates
A0
PCA8534A
A1
PCA8534A
V DD
V
A1
DD
A2
A2 SA0
V LCD
SA0
V
LCD
V
SS
V
SS
60 segment drives
Figure
60 segment drives
4 backplanes
BP0 to BP3
BP0 to BP3
(open-circuit)
PCA8534A
23.
© NXP B.V. 2010. All rights reserved.
LCD PANEL
013aaa271
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