PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 21

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PCA8534AH-Q900

Manufacturer Part Number
PCA8534AH-Q900
Description
Universal LCD driver for low multiplex rates
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PCA8534A_2
Product data sheet
7.16.5 I
7.16.6 Input filters
7.16.7 I
Acknowledgement on the I
The PCA8534A acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to V
applications A0, A1, and A2 are tied to V
no two devices with a common I
subaddress.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
PCA8534A. The entire I
Table 8.
Bit
2
2
2
Fig 14. Acknowledgement of the I
C-bus slave address, on the transferred command data and on the hardware
C-bus controller
C-bus protocol
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
2
C-bus slave addresses (0111 000 and 0111 001) are used to address the
by transmitter
data output
by receiver
data output
SCL from
Slave address
7
MSB
0
I
2
master
C slave address byte
All information provided in this document is subject to legal disclaimers.
SS
2
condition
6
1
which defines the hardware subaddress 0. In multiple device
C-bus master receiver. The only data output from the PCA8534A are
START
S
Rev. 02 — 1 June 2010
2
C-bus slave address byte is shown in
2
C-bus is illustrated in
2
C-bus slave receiver. It does not initiate I
5
1
2
C-bus slave address have the same hardware
2
1
C-bus
4
1
SS
Universal LCD driver for low multiplex rates
or V
2
DD
Figure
3
0
using a binary coding scheme, so that
14.
not acknowledge
2
0
acknowledge
Table
8
PCA8534A
acknowledgement
8.
clock pulse for
2
1
SA0
C-bus transfers or
© NXP B.V. 2010. All rights reserved.
9
mbc602
0
LSB
R/W
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