PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 14

• Manufacturer Part Number: PCA8534AH-Q900
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA8534A_2
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
7.9 Backplane outputs
The internal logic and the LCD drive signals of the PCA8534A are timed by the frequency
f
f
The internal oscillator is enabled by connecting pin OSC to pin V
output from pin CLK is the clock signal for any cascaded PCA8534A in the system.
Pin CLK is enabled as an external clock input by connecting pin OSC to V
frame signal frequency is determined by the clock frequency (f
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
The PCA8534A timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCA8534A in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock.
Table 6.
The display register holds the display data while the corresponding multiplex signals are
generated.
The LCD drive section includes 60 segment outputs (S0 to S59) which should be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 60 segment outputs are required, the unused segment outputs must be left
open-circuit.
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
Frame frequency
clk
clk(ext)
f
•
fr
, which equals either the built-in oscillator frequency f
In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
=
. The clock frequency f
f
------- -
24
clk
LCD frame frequencies
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 1 June 2010
clk
determines the LCD frame frequency (f
Universal LCD driver for low multiplex rates
Nominal frame frequency (Hz)
64
osc
or the external clock frequency
clk
).
SS
PCA8534A
. In this case, the
fr
© NXP B.V. 2010. All rights reserved.
).
DD
. The LCD
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