PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 23
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PCA8534AH-Q900
Manufacturer Part Number
PCA8534AH-Q900
Description
Universal LCD driver for low multiplex rates
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCA8534AH-Q900.pdf
(44 pages)
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NXP Semiconductors
PCA8534A_2
Product data sheet
7.17 Command decoder
Table 9.
The command bytes and control bytes are also acknowledged by all addressed
PCA8534A connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCA8534A. After the last display byte, the I
Alternatively a START may be issued to RESTART I
The command decoder identifies command bytes that arrive on the I
five commands:
Table 10.
Bit
7
6
5 to 0
Command
Bit
Mode-set
Load-data-pointer
Device-select
Bank-select
Blink-select
Symbol
CO
RS
-
Control byte description
Definition of commands
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
Rev. 02 — 1 June 2010
Operation Code
7
1
0
1
1
1
6
1
P6
1
1
1
Description
continue bit
register selection
not relevant
last control byte
control bytes continue
command register
data register
5
0
P5
1
1
1
Universal LCD driver for low multiplex rates
2
4
0
P4
0
1
1
C-bus master issues a STOP condition (P).
3
E
P3
0
1
0
2
C-bus access.
2
B
P2
A2
0
A
1
M1
P1
A1
I
BF1
PCA8534A
2
C-bus. There are
© NXP B.V. 2010. All rights reserved.
M0
P0
0
A0
O
BF0
Reference
Table 11
Table 12
Table 13
Table 14
Table 15
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