PCA85133 NXP [NXP Semiconductors], PCA85133 Datasheet - Page 14

• Manufacturer Part Number: PCA85133
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA85133_1
Product data sheet
7.10 Display RAM
7.8 Segment outputs
7.9 Backplane outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. When less
than 80 segment outputs are required the unused segment outputs must be left
open-circuit.
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
If less than four backplane outputs are required the unused outputs can be left
open-circuit.
The display RAM is a static 80
bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs and between the individual bits of a RAM word and
the backplane outputs. The display RAM bit map
correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which
correspond with the segment outputs S0 to S79. In multiplexed LCD applications the
segment data of the first, second, third and fourth row of the display RAM are
time-multiplexed with BP0, BP1, BP2, and BP3 respectively.
Fig 9.
•
•
•
•
In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
display RAM rows/
backplane outputs
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Display RAM bitmap
rows
(BP)
0
1
2
3
Rev. 1 — 23 October 2009
0
1
2
4 bit RAM which stores LCD data. A logic 1 in the RAM
3
display RAM addresses/segment outputs (S)
4
Universal LCD driver for low multiplex rates
columns
Figure 9
shows rows 0 to 3 which
75
PCA85133
76
© NXP B.V. 2009. All rights reserved.
77
013aaa214
78
79
14 of 44