PCF8562TT-2 NXP [NXP Semiconductors], PCF8562TT-2 Datasheet - Page 7

• Manufacturer Part Number: PCF8562TT-2
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8562
Product data sheet
7.1 Power-On Reset (POR)
7.2 LCD bias generator
7.3 LCD voltage selector
The host microcontroller maintains the 2-line I
PCF8562. The internal oscillator is enabled by connecting pin OSC to pin V
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(V
At power-on the PCF8562 resets to the following starting conditions:
Remark: Do not transfer data on the I
the reset action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between V
bypassed by switch if the
configuration is selected. The LCD voltage can be temperature compensated externally,
using the supply to pin V
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
V
Fig 4.
LCD
•
•
•
•
•
•
•
DD
All backplane and segment outputs are set to V
The selected drive mode is: 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
Display is disabled
, V
and the resulting discrimination ratios (D) are given in
V
SS
V
SS
DD
CONTROLLER
PROCESSOR/
2
The resistance of the power lines must be kept to a minimum.
Typical system configuration
, and V
C-bus interface is initialized
MICRO-
MICRO-
HOST
R ≤
All information provided in this document is subject to legal disclaimers.
LCD
2C
t
r
) and the LCD panel chosen for the application.
b
Rev. 6 — 16 June 2011
LCD
1
⁄
2
.
bias voltage level for the 1:2 multiplex drive mode
OSC
SDA
SCL
10
11
15
2
16
C-bus for at least 1 ms after a power-on to allow
A0
14
17
Universal LCD driver for low multiplex rates
A1
V
PCF8562
DD
18
2
C-bus communication channel with the
A2
21
V
19
LCD
LCD
1
SA0
⁄
LCD
3
20
bias
and V
V
SS
32 segment drives
4 backplanes
SS
Table
. The center impedance is
5.
PCF8562
© NXP B.V. 2011. All rights reserved.
LCD PANEL
(up to 128
elements)
001aac264
SS
. The
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