pcf8562 NXP Semiconductors, pcf8562 Datasheet
pcf8562
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pcf8562 Summary of contents
Page 1
... The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments. The PCF8562 is compatible with most microprocessors/microcontrollers and communicates via a ...
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... BLINKER TIMEBASE COMMAND POWER-ON DECODER RESET 2 I C-BUS CONTROLLER 19 SA0 Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates S0 to S31 DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY RAM 40 4-BIT ...
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... LCD segment output 7 LCD segment output 8 LCD segment output 9 LCD segment output C-bus serial data input and output C-bus serial clock input Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates 48 S22 47 S21 46 S20 45 S19 44 S18 43 S17 42 S16 ...
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... LCD segment output 42 LCD segment output 43 LCD segment output 44 LCD segment output 45 LCD segment output 46 LCD segment output 47 LCD segment output 48 LCD segment output Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates © NXP B.V. 2007. All rights reserved ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF8562 depend on the number of active backplane outputs required. A selection of display configurations is shown in these configurations can be implemented in the typical system shown in Table 3 ...
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... NXP Semiconductors 6.1 Power-on reset At power-on the PCF8562 resets to the following starting conditions: • All backplane outputs are set to V • All segment outputs are set to V • Drive mode ‘ multiplex with • Blinking is switched off • Input and output bank selectors are reset (as defined in • ...
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... N V --------------------------------------------------------------- – V ---------------------------------- - and is determined by the formula: 1 bias 2.449 V off(rms) off rms 3 = 2.309 V off(rms when bias is used. 3 PCF8562 – ------------ - (1) 1 bias is ---------- = 1.528. 3 LCD © NXP B.V. 2007. All rights reserved. ...
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... V state1 Sn BP0 on(rms) Rev. 02 — 22 January 2007 Universal LCD driver for low multiplex rates T frame LCD segments state 1 state 2 (on) (off) 001aac312 001aac313 ; V ( (t) V (t); V LCD state2 Sn+1 BP0 off(rms) PCF8562 Figure © NXP B.V. 2007. All rights reserved ...
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... LCD V LCD V ( ( 0.791V state1 Sn BP0 on(rms 0.354V off(rms) LCD Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates 1 1 bias or bias as shown frame LCD segments state 1 state 2 001aac314 001aac315 ; V ( (t) V (t); ...
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... LCD LCD V LCD V ( ( 0.745V state1 Sn BP0 on(rms 0.333V off(rms) LCD Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates T frame LCD segments state 1 state 2 001aac316 001aac317 ; V ( (t) V (t); LCD state2 Sn+1 BP1 1 bias 3 © NXP B.V. 2007. All rights reserved. ...
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... LCD V LCD V ( ( 0.638V state1 Sn BP0 on(rms 0.333V off(rms) LCD Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates T frame LCD segments state 1 state 2 001aac319 ; V ( (t) V (t); LCD state2 Sn BP1 001aac318 © NXP B.V. 2007. All rights reserved. ...
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... When four backplanes are provided in the LCD, the multiplex drive mode applies (see Figure 8). PCF8562_2 Product data sheet Universal LCD driver for low multiplex rates Rev. 02 — 22 January 2007 PCF8562 © NXP B.V. 2007. All rights reserved ...
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... LCD LCD V LCD = 0.577V ; V ( (t) on(rms) LCD state2 Sn Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates LCD segments state 1 state 2 001aac320 001aac321 V (t 0.333V BP1 off(rms) LCD © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 6.5 Oscillator 6.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V 6.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to V The LCD frame signal frequency is determined by the clock frequency (f A clock signal must always be supplied to the device ...
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... Fig 9. Display RAM bit-map showing direct relationship between display RAM addresses When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets ...
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Data pointer drive mode LCD segments LCD backplanes BP0 static ...
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... The PCF8562 includes a RAM bank switching feature in the static and drive modes. In the static drive mode, the Bank Select command may request the contents of bit selected for display instead of the contents of bit 0 ...
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... NXP Semiconductors 6.15 Blinker The PCF8562 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the Blink command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 5 ...
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... SDA SCL data line stable; data valid Figure 12). S START condition MASTER SLAVE TRANSMITTER/ TRANSMITTER/ RECEIVER RECEIVER Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Figure 11). change of data allowed mba607 P STOP condition Figure 13). SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER © ...
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... S START condition 2 C-bus 2 C-bus controller 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCF8562 are Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Figure 14). not acknowledge acknowledge 2 8 clock pulse for ...
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... C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8562. The least significant bit of the slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to a read access. ...
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... When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8562 are defined in Table 6. Definition of PCF8562 commands ...
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... RAM bits 0 and 1 RAM bits 2 and 3 Bank select option 2 (output) Mode RAM bits 0 and 1 RAM bits 2 and 3 Blink option 1 Mode set option 3 Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Bit Bit Bit P5 P4 ...
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... Number of devices PCF8562_2 Product data sheet SYNC contact resistance Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Table Maximum contact resistance 6000 2200 1200 700 © NXP B.V. 2007. All rights reserved. 16. ...
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... V DD OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S31 V SS Rev. 02 — 22 January 2007 PCF8562 SCL V SS SDA LCD V SS 001aac269 © NXP B.V. 2007. All rights reserved ...
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... Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA. PCF8562_2 Product data sheet Universal LCD driver for low multiplex rates Conditions pins CLK, SYNC, SA0, OSC pins SCL and SDA pins S31 to S0, BP3 to BP0 Rev. 02 — 22 January 2007 PCF8562 Min Max Unit 0.5 +6 0.5 +7 ...
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... [ 1.0 1.3 [ 100 - 100 - [5] - 1.5 [5] - 6.0 2 C-bus inactive. limiting values given in i PCF8562 Max Unit 5 +100 mV +100 Section 9; © NXP B.V. 2007. All rights reserved. ...
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... LCD - - 1.3 - 0.6 - 0.6 - 1 400 kHz - - < 400 kHz - - - - - - 100 - 1.5 k SDA, 0.5V DD SCL ( 001aac267 PCF8562 Max Unit 2640 400 kHz - 0.3 s 1.0 s 0.3 s 400 and V with © NXP B.V. 2007. All rights reserved. ...
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... Product data sheet 1/f CLK t CLKH CLK SYNC t PD(SYNC BUF LOW t HD;STA C-bus timing waveforms Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates t CLKL t PD(SYNC) t SYNCL t PD(LCD HD;DAT t HIGH t SU;STA © NXP B.V. 2007. All rights reserved. ...
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... Rev. 02 — 22 January 2007 Universal LCD driver for low multiplex rates detail 0.8 0.50 1 0.25 0.08 0.4 0.35 EUROPEAN PROJECTION PCF8562 SOT362 0.8 8 0.1 o 0.4 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...
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... Package placement • Inspection and repair • Lead-free soldering versus PbSn soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCF8562_2 Product data sheet Universal LCD driver for low multiplex rates Rev. 02 — 22 January 2007 PCF8562 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 22. Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Figure 22) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2007. All rights reserved. time 001aac844 ...
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... LCD frame frequency changed from 64 kHz added column for ‘topside mark’ Product data sheet Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates Change notice Supersedes - PCF8562_1 - - © NXP B.V. 2007. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates © NXP B.V. 2007. All rights reserved ...
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... Universal LCD driver for low multiplex rates Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 Handling information . . . . . . . . . . . . . . . . . . . 31 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction to soldering Wave and reflow soldering . . . . . . . . . . . . . . . 31 Wave soldering Reflow soldering Revision history . . . . . . . . . . . . . . . . . . . . . . . 34 Legal information . . . . . . . . . . . . . . . . . . . . . . 35 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Contact information . . . . . . . . . . . . . . . . . . . . 35 Contents Date of release: 22 January 2007 Document identifier: PCF8562_2 All rights reserved. ...