PCF8562TT-2 NXP [NXP Semiconductors], PCF8562TT-2 Datasheet - Page 19

• Manufacturer Part Number: PCF8562TT-2
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8562
Product data sheet
7.10.1 Data pointer
7.10.2 Subaddress counter
The following applies to
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
If an I
The data pointer should be re-written prior to further RAM accesses.
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed to take place only when the content of the subaddress counter
matches with the hardware subaddress applied to A0, A1, and A2. The subaddress
counter value is defined by the device-select command (see
the subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The hardware subaddress must not be changed while the device is being accessed on the
I
2
•
•
•
•
•
•
•
•
C-bus interface.
In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see
In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
2
C-bus data access is terminated early then the state of the data pointer is unknown.
All information provided in this document is subject to legal disclaimers.
Section
Rev. 6 — 16 June 2011
Figure
Figure
7.10.3).
12:
12.
Universal LCD driver for low multiplex rates
Table
12). Following this command,
Table
13). If the content of
PCF8562
© NXP B.V. 2011. All rights reserved.
19 of 43