CY7C64013 CYPRESS [Cypress Semiconductor], CY7C64013 Datasheet - Page 9

• Manufacturer Part Number: CY7C64013
• Description: Full-Speed USB (12 Mbps) Function
• Manufacturer: CYPRESS [Cypress Semiconductor]

4.0
4.1
Table 4-1. Pin Assignments
4.2
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write
(IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation
or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written
with ‘0.’
Table 4-2. I/O Register Summary
Document #: 38-08001 Rev. **
Name
D+[0], D–[0]
P0
P1
P2
P3
DAC
XTAL
XTAL
V
V
GND
V
NC
Port 0 Data
Port 1 Data
Port 2 Data
Port 3 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
PP
CC
REF
IN
OUT
Register Name
Pin Assignments
I/O Register Summary
Product Summary Tables
OUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
IN
10, 14, 11, 15,
12, 16, 13, 17
28-Pin SOIC
19, 9, 20, 8,
25, 27, 26
23, 5, 24
P0[7:0]
P1[2:0]
P2[6:2]
P3[2:0]
4, 22
6, 7
21
18
28
2
1
3
I/O Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
11, 15, 12, 16,
13, 17, 14, 18
28-Pin PDIP
20, 10, 21,
26, 4, 27
24, 6, 25
P0[7:0]
P1[2:0]
P2[6:2]
P3[2:0]
9, 23
5, 22
7, 8
19
28
2
1
3
Read/Write
R/W
R/W
R/W
R/W
W
W
W
W
20, 26, 21, 27,
18, 32, 17, 33,
13, 37, 12, 39,
48-Pin SSOP
22, 28, 23, 29
15, 35, 14, 36
19, 25, 24, 31
11, 16, 34, 40
4, 45, 47, 46
10, 41, 7, 42
6, 43, 5, 44,
DAC[7,2:0]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
7, 8
30
48
38
2
1
3
GPIO Port 0 Data
GPIO Port 1 Data
GPIO Port 2 Data
GPIO Port 3 Data
Interrupt Enable for Pins in Port 0
Interrupt Enable for Pins in Port 1
Interrupt Enable for Pins in Port 2
Interrupt Enable for Pins in Port 3
Description
Upstream port, USB differential data.
GPIO Port 0 capable of sinking 7 mA (typical).
GPIO Port 1 capable of sinking 7 mA (typical).
GPIO Port 2 capable of sinking 7 mA (typical). HAPI
is also supported through P2[6:2].
GPIO Port 3, capable of sinking 12 mA (typical).
DAC Port with programmable current sink outputs.
DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7,2] have a programmable sink current
range of 0.2 to 1.0 mA typical.
6-MHz crystal or external clock input.
6-MHz crystal out.
Programming voltage supply, tie to ground during nor-
mal operation.
Voltage supply.
Ground.
External 3.3V supply voltage for the differential data
output buffers and the D+ pull-up.
No Connect.
Function
CY7C64013
CY7C64113
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