CY7C64013 CYPRESS [Cypress Semiconductor], CY7C64013 Datasheet - Page 23

• Manufacturer Part Number: CY7C64013
• Description: Full-Speed USB (12 Mbps) Function
• Manufacturer: CYPRESS [Cypress Semiconductor]

13.0
The I
multi-master modes of operation. The I
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I
The I
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 16.8.
The I
(Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I
Register should only be monitored after the I
read misleading bit status if a transaction is underway.
The I
1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I
used to set the locations of the configurable I
0 of the I
regardless of the settings of the GPIO Configuration Register.The electrical characteristics of the I
same as that of GPIO ports 1 and 2. Note that the I
All control of the I
The I
Table 13-1. I
Document #: 38-08001 Rev. **
I
2
Bit
C Data 7
MSTR
0
1
2
3
4
5
6
7
Mode
2
2
2
2
2
R/W
C compatible interface consists of two registers, an I
C compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I
C Status and Control register bits are defined in Table 13-1, with a more detailed description following.
C compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
7
7
2
I
C Status & Control Register, the two LSB bits ([1:0]) of the corresponding GPIO port are placed in Open Drain mode,
2
I
Received Stop
ARB Lost/Restart
Addr
ACK
Xmit Mode
Continue / Busy
MSTR Mode
2
C Compatible Controller
C Enable
2
C Status and Control Register Bit Definitions
2
C clock and data lines is performed by the I
I
Continue/
2
C Data 6
Name
2
Busy
R/W
C compatible bus idle if necessary.
6
6
Figure 13-1. I
Figure 13-2. I
I
2
C Data 5
Mode
R/W
Xmit
2
5
5
Write to 1 to enable I
operate normally.
Reads 1 only in slave receive mode, when I
ACK the last transaction).
Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
Write 1 to indicate ready for next transaction.
Reads 1 when I
complete.
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
C compatible block functions by handling the low-level signaling in hardware, and issuing
2
C Data Register 0x29 (separate read/write registers)
2
2
C interrupt, as all bits are valid at that time. Polling this register at other times could
2
C Status and Control Register 0x28 (read/write)
C compatible pins. Once the I
I
OL
2
C Data 4
ACK
R/W
(max) is 2 mA @ V
2
4
4
C compatible block is busy with a transaction, 0 when transaction is
2
C Data Register (Figure 13-1) and an I
2
C compatible function. When cleared, I
2
C compatible block.
I
2
C Data 3
Addr
R/W
3
3
OL
2
= 2.0 V for ports 1 and 2.
Description
C compatible functionality is enabled by setting bit
2
C SDA data is connected to bit 1 of GPIO port
2
I
ARB Lost/
C Stop bit detected (unless firmware did not
2
Restart
C Data 2
R/W
2
2
2
C Configuration Register, which is
2
C Status and Control Register
2
C compatible interface is the
I
Received
2
2
C Data 1
C compatible GPIO pins
Stop
R/W
1
1
2
C Status and Control
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I
2
Enable
C Data 0
R/W
I
2
0
0
C