CY7C64013 CYPRESS [Cypress Semiconductor], CY7C64013 Datasheet - Page 24

• Manufacturer Part Number: CY7C64013
• Description: Full-Speed USB (12 Mbps) Function
• Manufacturer: CYPRESS [Cypress Semiconductor]

MSTR Mode: Setting this bit causes the I
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes are
initiated by setting the Continue bit, as described below.
In master mode, the I
or receive state. The I
results in the clearing of this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the
chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the external
master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I
Continue / Busy: This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin.
In other words, the bit has responded to an interrupt request and has completed the required update or read of the data register.
During a read this bit indicates if the hardware is busy and is locking out additional writes to the I
This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I
interrupt, the I
to make one control register write without the need to check the Busy bit.
Xmit Mode: This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clear this
bit for receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I
The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases always cause transmit
mode for the first byte.
ACK: This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I
During transmits (Xmit Mode=1), this bit should be cleared.
Addr: This bit is set by the I
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has
lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
ARB Lost/Restart: This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along
with the Continue and MSTR Mode bits) to perform an I
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set
if the firmware terminates the I
in receive mode if firmware sets the Continue bit and clears the ACK bit.
I
cleared, these pins are free to function as GPIOs. In I
of the GPIO configuration setting.
14.0
The CY7C64x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate
data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I
Configuration Register (Figure 12-1), bits 1 and 0.
Signals are provided on Port 2 to control the HAPI interface. Table 14-1 describes these signals and the HAPI control bits in the
HAPI/I
overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3
OFF in Figure 9-1).
Document #: 38-08001 Rev. **
2
C Enable: Set this bit to override GPIO definition with I
2
2
C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (0x08) to be
C compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I
Hardware Assisted Parallel Interface (HAPI)
2
C compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the firmware
2
C compatible block generates the clock (SCK), and drives the data line as required depending on transmit
2
C compatible block performs any required arbitration and clock synchronization. The loss of arbitration
2
C compatible block during the first byte of a slave receive transaction, after an I
2
C transaction by not acknowledging the previous byte transmitted on the I
2
C compatible block to initiate a master mode transaction by sending a start bit and
2
C compatible mode, the two pins operate in open drain mode, independent
2
C restart sequence. The I
2
C compatible function on the two I
2
C Stop bit is generated.
2
C target address for the restart must be written
2
C compatible bus at the ACK bit time.
2
C compatible pins. When this bit is
2
C Status and Control register.
2
C compatible bus, e.g.,
CY7C64013
CY7C64113
2
2
C address packet.
C start or restart.
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2
2
C
C