PNX1300 Philips, PNX1300 Datasheet - Page 354

• Manufacturer Part Number: PNX1300
• Description: Media Processors
• Manufacturer: Philips

Philips Semiconductors
Floating-point compare not equal
SYNTAX
FUNCTION
DESCRIPTION
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point operation but can only be reset by an explicit
occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the
same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
[ IF rguard ] fneq rsrc1 rsrc2
if rguard then {
}
if (float)rsrc1 != (float)rsrc2 then
else
fneq
fneqflags
rdest
rdest
fneq
operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is not equal to the second
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
1
0
operation computes the exception flags that would result from an individual
fneq r30 r40
fneq r30 r30
IF r10 fneq r60 r30
IF r20 fneq r60 r30
fneq r30 r60
fneq r30 r61
fneq r50 r55
fneq r60 r65
fneq r50 r50
rdest
writepcsw
fneq
Operation
causes an IEEE exception, the corresponding exception
r80
r90
r120
r121
r125
r126
r127
PRELIMINARY SPECIFICATION
operation. The update of the PCSW exception flags
r100
r110
PNX1300/01/02/11 DSPCPU Operations
r80
r90
no change, since guard is false
r110
r120
r121
r125
r126
r127
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
1
0
ineq feql fneqflags
1
1
0
1
1, IFZ flag set
0
readpcsw writepcsw
ATTRIBUTES
SEE ALSO
Result
fneq
.
fneq
fcomp
150
No
—
2
1
3
A-56