PNX1300 Philips, PNX1300 Datasheet - Page 308

• Manufacturer Part Number: PNX1300
• Description: Media Processors
• Manufacturer: Philips

Philips Semiconductors
Arithmetic shift right
SYNTAX
FUNCTION
DESCRIPTION
amount, and rsrc1 is arithmetically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as a
shift by 32 or more bits. The MSB (sign bit) of rsrc1 is replicated as needed to fill vacated bits from the left.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
r30 = 0x7008000f, r20 = 1
r30 = 0x7008000f, r42 = 2
r10 = 0, r30 = 0x7008000f, r44 = 4
r20 = 1, r30 = 0x7008000f, r44 = 4
r40 = 0x80030007, r44 = 4
r30 = 0x7008000f, r45 = 0x1f
r30 = 0x8008000f, r45 = 0x1f
r30 = 0x7008000f, r45 = 0x20
r30 = 0x8008000f, r45 = 0x20
r30 = 0x8008000f, r45 = 0x23
As shown below, the
The
[ IF rguard ] asr rsrc1 rsrc2
if rguard then {
}
rsrc1
n
rdest<31:31–n>
rdest<30–n:0>
if rsrc2<31:5> != 0 {
}
rdest <- rsrc1<31>
asr
S
31
rsrc2<4:0>
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
rsrc1<30:n>
rsrc1<31>
Intermediate result
(example: n = 3)
asr
operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
rdest
asr r30 r20
asr r30 r42
IF r10 asr r30 r44
IF r20 asr r30 r44
asr r40 r44
asr r30 r45
asr r30 r45
asr r30 r45
asr r30 r45
asr r30 r45
31
S
S
S
S
S
S
28
S
S
rdest
0
Operation
Right shifter
r50
r60
r90
r100
r100
r100
r100
r100
32 bits from rsrc1
PRELIMINARY SPECIFICATION
rsrc2
r70
r80
31
PNX1300/01/02/11 DSPCPU Operations
0
asl asli asri lsl lsli lsr
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r50
r60
no change, since guard is false
r80
r90
r100
r100
r100
r100
r100
0x38040007
0x1c020003
0x07008000
0xf8003000
0x00000000
0xffffffff
0x00000000
0xffffffff
0xffffffff
lsri rol roli
ATTRIBUTES
SEE ALSO
rsrc2
Result
shifter
1, 2
No
18
—
2
1
asr
0
A-10