PNX1300 Philips, PNX1300 Datasheet - Page 185

• Manufacturer Part Number: PNX1300
• Description: Media Processors
• Manufacturer: Philips

Philips Semiconductors
terface must be lowered to account for extra propagation
delay due to the excessive loading on the interface sig-
nals (see
The following rules apply to memory rank design:
• All devices in a rank must be of the same type.
• All ranks must be a power of two in size.
• All ranks must be of equal size.
Table 12-4
tem designs.
Table 12-4.
Refer to the TM-1100 Databook for smaller memory con-
figurations.
Note:
• Some of these configurations may not be economi-
(MB)
Size
16
24
32
48
64
cally attractive due to the price premium.
8
1. However MM_CONFIG.SIZE may be 16 MB (i.e.
2. However MM_CONFIG.SIZE is 32 MB (i.e. 7).
6). Refer to
the two possible connection details.
Ranks
Section 12.13, “Output Driver
1
1
1
1
2
1
1
1
2
3
2
2
4
3
4
lists some examples of 32-bit memory sys-
1
1
2
Examples of 32-bit Memory Configurations
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
one 4 512K 32 SDRAM
two 2 512K 16 SDRAM
two 2 512K 16 SDRAM
Rank Configurations
Figure 12-10
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
one 4 1M 32 SDRAM
two 4 1M 16 SDRAM
two 4 2M 16 SDRAM
two 4 1M 16 SDRAM
two 4 1M 16 SDRAM
two 4 4M 16 SDRAM
four 2 1M 8 SDRAM
four 4 2M 8 SDRAM
and
Figure 12-11
Capacity”).
Max.
MHz
166
166
183
183
183
183
166
183
166
166
183
166
166
183
166
for
MB/s
Peak
664
664
732
732
732
732
664
732
664
664
732
664
664
732
664
• ‘Max. MHz’ refers to the memory interface/SDRAM
Table 12-4
designs.
Table 12-5.
12.6
Memory system parameters are determined by the con-
tents of two configuration registers, MM_CONFIG and
PLL_RATIOS.
these registers, and
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read.
MM_CONFIG and PLL_RATIOS are loaded from the
boot EEPROM, as described in
EEPROM Contents.”
ory interface is held in reset state. After the memory in-
terface is released from reset, the contents of these reg-
isters cannot be altered.
These registers are visible in MMIO space. They can be
read, but writes have no effect.
12.6.1
The MM_CONFIG register tells the memory interface
how to use the local DRAM memory. The fields in this
register tell the interface the rank size and the refresh
rate of the memory.
functions.
REFRESH (Refresh interval). The 16-bit REFRESH
field specifies the number of memory-system clock cy-
cles between refresh operations. The default value of
this field is 1000 (0x03E8). See
for more information.
BW (Bus Width). If set to ‘0’ then the memory interface
data bus width is 32 bits. If set to ‘1’ then the memory in-
terface data bus width is 16 bits.
SIZE (Rank size). The 3-bit SIZE field specifies the size
of each rank of DRAM. Each rank must be the size spec-
ified by SIZE. The default is a rank size of 4MB. Refer to
Table 12-7
PRELIMINARY SPECIFICATION
(MB)
Size
1.
2.
16
32
speed, not the PNX1300 core operating frequency.
The maximum MHz also depends on the device
being used, i.e. PNX1300, PNX1311 or PNX1302.
Refer to
operating speeds.
8
1
2
However MM_CONFIG.SIZE is set to 8 MB (i.e. 5)
However MM_CONFIG.SIZE is set to 8 MB (i.e. 5)
MEMORY SYSTEM PROGRAMMING
Ranks
MM_CONFIG Register
lists some example of 32-bit memory system
1
1
1
for the interpretation of this field.
Section 1.9.7.10 on page 1-18
Supported 16-bit Memory Configurations
Table 12-6
Rank Configurations
one 4 1M 16 SDRAM
one 4 2M 16 SDRAM
one 4 4M 16 SDRAM
Figure 12-2
During this boot process, the mem-
Table 12-8
SDRAM Memory System
describes the function of
Section 12.11, “Refresh,”
shows their formats.
Section 13.4, “Detailed
summarizes the field
Max.
MHz
183
183
183
for maximum
MB/s
Peak
732
732
732
12-3