lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet - Page 5

• Manufacturer Part Number: lc51024vg
• Description: 3.3v In-system Programmable Superbig, Superwide High Density Plds Tm Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Macrocell
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks
and control logic to allow combinatorial or registered operation.
The macrocells each have two outputs, which can be fed to the GRP and I/O cell. This dual or concurrent output
capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function
for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O
cell facilitates efficient use of the macrocell to construct high-speed input registers.
Macrocell registers can be clocked from one of several global or product term clocks available on the device. A glo-
bal and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers
directly. Reset and preset for the macrocell register is provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 5 is a graphical rep-
resentation of the ispMACH 5000B macrocell.
Figure 5. ispMACH 5000B Macrocell
I/O Cell
The ispMACH 5000B I/O cell provides a high degree of flexibility. It includes the sysIO feature and an enhanced
output enable MUX for optimal performance both on- and off-chip. The sysIO feature allows I/O cells to be config-
ured to different I/O standards, drive strengths and slew rates. The enhanced output enable MUX provides up to 14
different output enable choices per I/O cell.
The I/O cell contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input
buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-friendly latch.
The I/O cell receives its input from its associated macrocell. The I/O cell has a feedback line to its associated mac-
rocell and a direct path to the GRP.
The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four shared
PTOE signals, PTOE, the two GOE signals. The OE MUX also has the ability to choose either the true or inverse of
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From
GRP
AND Array
Speed/
Power
Dual-OR Array
Shared PT Reset
Shared PT Clock
PTSA Bypass
Global Reset
PT Preset
PT Reset
PT Clock
PTSA
CLK0
CLK1
CLK2
CLK3
5
ispMACH 5000B Family Data Sheet
Macrocell
D
Clk En
Clk
P
R/L
R
Q
PT OE to
I/O Block
From
I/O Cell
Output
to I/O Block
GRP