lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet
lc51024vg
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September 2003 Features High Speed Logic Implementation • SuperWIDE 68-input logic block • product terms per output • Single-level Global Routing Pool (GRP) TM sysIO Capability • LVCMOS 1.8, 2.5 and 3.3 • LVTTL • SSTL 2 ...
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Lattice Semiconductor Figure 1. Functional Block Diagram I/O Bank 0 Generic VCCO0 VREF0 GCLK0 TOE GCLK1 Generic VCCO1 VREF1 I/O Bank 1 The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form ...
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Lattice Semiconductor and complement form for every product term. The three control product terms are used for shared reset, clock and output enable functions. AND-Array The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs ...
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Lattice Semiconductor Figure 3. ispMACH 5000B Dual-OR Array From PT0 From PT1 From PT2 From PT3 From PT4 Product Term Sharing Array The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array and 32 outputs directly ...
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Lattice Semiconductor Macrocell The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks and control ...
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Lattice Semiconductor each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tri- stating of the outputs for testing purposes. The four Shared PTOE signals are derived from ...
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Lattice Semiconductor For more information on the sysIO capability, please refer to technical note number TN1000, sysIO Design and Usage Guidelines available on the Lattice web site at www.latticesemi.com. Table 2. ispMACH 5000B Supported I/O Standards LVTTL LVCMOS 3.3 LVCMOS ...
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Lattice Semiconductor Figure 7. ispMACH 5000B Global Clock MUX GCLK0 VREF0 GCLK1 VREF1 VREF2 GCLK2 VREF3 GCLK3 Power Management The ispMACH 5000B devices provide unique power management controls. The device has two power settings, high power and low power, on ...
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Lattice Semiconductor that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication interface through which ISP is achieved, customers get the benefi standard, well-defined interface. The ispMACH 5000B devices ...
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Lattice Semiconductor Absolute Maximum Ratings Supply Voltage -0.5 to 4.05V CC Output Supply Voltage ...
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Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input I/O Input I/O Weak Pull-up Resistor Current I/O Weak Pull-down Resistor Current Bus ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVTTL LVCMOS 3.3 1 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 AGP-1X SSTL 3, Class I, II SSTL 2, Class I, II CTT 3.3 CTT 2.5 HSTL GTL+ 1. Software default setting. V (V) ...
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Lattice Semiconductor sysIO DC Electrical Characteristics V IL Input/Output Standard Min (V) Max (V) LVCMOS 3.3 -0.3 LVTTL -0.3 1 LVCMOS 2.5 -0.3 LVCMOS 2.5 -0.3 LVCMOS 1.8 -0.3 PCI 3.3 -0.3 AGP-1X -0.3 SSTL3 class I -0.3 V REF ...
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Lattice Semiconductor ispMACH 5128B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...
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Lattice Semiconductor ispMACH 5256B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...
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Lattice Semiconductor ispMACH 5384B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...
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Lattice Semiconductor ispMACH 5512B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...
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Lattice Semiconductor Timing Model The task of determining the timing through the ispLSI 5000B family, just as any CPLD, is relatively simple. The tim- ing model provided in Figure 8 shows the specific delay paths. Once the implementation of a ...
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Lattice Semiconductor ispMACH 5128B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...
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Lattice Semiconductor ispMACH 5256B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...
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Lattice Semiconductor ispMACH 5384B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...
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Lattice Semiconductor ispMACH 5512B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...
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Lattice Semiconductor ispMACH 5128B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI GCLK_IN LVCMOS18_in t t RST, GOE GCLK_IN LVCMOS25_in t t RST, GOE t , ...
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Lattice Semiconductor ispMACH 5128B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4A_out EN, DIS, BUF LVCMOS33_5mA_out ...
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Lattice Semiconductor ispMACH 5128B Timing Adders (Cont). Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE Note: Open drain timing is the same as corresponding LVCMOS timing. -4 Base Parameter Min. Max. ...
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Lattice Semiconductor ispMACH 5256B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI GCLK_IN LVCMOS18_in t t RST, GOE GCLK_IN LVCMOS25_in t t RST, GOE t , ...
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Lattice Semiconductor ispMACH 5256B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4A_out EN, DIS, BUF LVCMOS33_5mA_out ...
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Lattice Semiconductor ispMACH 5256B Timing Adders (Cont). Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE 4 t ROUTE 5 t ROUTE 6 t ROUTE 7 t ROUTE Note: Open drain timing ...
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Lattice Semiconductor ispMACH 5384B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI LVCMOS18_in t t IN, GCLK_IN RST, GOE LVCMOS25_in t t IN, GCLK_IN RST, GOE LVCMOS33_in t t IN, ...
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Lattice Semiconductor ispMACH 5384B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4mA_out EN, DIS, BUF LVCMOS33_5mA_out ...
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Lattice Semiconductor ispMACH 5384B Timing Adders (Cont.) Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE 4 t ROUTE 5 t ROUTE 6 t ROUTE 7 t ROUTE 8 t ROUTE 9 ...
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Lattice Semiconductor ispMACH 5512B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI t t IN, GCLK_IN, LVCMOS18_in t t RST, GOE t t IN, GCLK_IN, LVCMOS25_in t t RST, GOE t t IN, GCLK_IN, ...
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Lattice Semiconductor ispMACH 5512B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4mA_out EN, DIS, BUF LVCMOS33_5mA_out ...
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Lattice Semiconductor ispMACH 5512B Timing Adders (Cont.) Adder Type t Input Adders IOI CLK0 t GCLK_IN CLK1 t GCLK_IN CLK2 t GCLK_IN CLK3 t GCLK_IN t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE ...
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Lattice Semiconductor Power Consumption ispMACH 5000B Typical I 600 500 400 300 200 100 0 0 Note: The devices are configured with maximum number of 16-bit counters, typical current at 2.5V, 25°C. Power Estimation Coefficients Device K0 ispMACH 5128B 0.0055 ...
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Lattice Semiconductor Switching Test Conditions Figure 9 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, volt- age, and other test conditions are shown in Table 3. Figure 9. Output Test Load, ...
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Lattice Semiconductor Signal Descriptions Signal Names TMS Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine. TCK Input - This pin is the Test Clock input pin, used to ...
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Lattice Semiconductor ispMACH 5000B Power Supply and NC Connections 1,2 Signal 128-Pin TQFP 208-Pin PQFP VCC 13, 45, 77, 109 11, 48, 74, 115, 152, 178 VCCO0 5, 120 5256B: 18, 189, 203 5384B/5512B: 7, 18, 189, 203 VCCO1 28, ...
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Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP Pin Number ...
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Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number ...
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Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 ...
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Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 127 128 ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP Pin Bank Number Number ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 ispMACH 5256B, 5384B, 5512B ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - - ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number T10 T11 T12 R10 P9 R11 T13 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - - L10 L11 K11 R15 P15 R16 P16 N14 N13 - - - - N15 N16 M16 M12 M13 M15 L16 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number H14 H13 H16 J10 J12 G16 G15 H12 G12 G13 - - - - F16 F15 F13 F14 F12 E16 G11 F11 F10 B11 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - C16 C15 D14 A14 C13 B13 - - A13 A12 A11 - - A10 C11 A9 D12 D11 B10 B9 E11 A8 D10 ...
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Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - ispMACH 5512B Logic Signal Connections: 484 fpBGA ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - - - - AA3 ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - AB3 Y6 AB4 Y7 AB5 V8 AA7 Y8 AB6 W8 AA8 Y10 - - U8 AB7 U9 AA9 W9 AB8 U10 AB9 V11 AA10 V10 AB10 - ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number W12 Y11 Y12 AB12 U12 AA12 - - - - Y13 AB13 W13 AA13 U13 AB14 V13 AA14 U14 AB15 Y15 AB16 - - AA15 W14 AB17 Y16 ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number AA19 V16 AB21 Y18 W18 AA20 W19 Y19 V19 - - - - Y21 W20 AA22 W21 Y22 V20 V21 W22 V18 U20 V22 U19 - - U17 ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number P17 P19 R21 T22 P21 N20 R22 N21 - - - - M18 N19 P22 M20 N22 N17 M19 M21 L19 L20 - - - - M17 M22 ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number J19 J22 J21 - - F22 E22 E19 E20 D22 D21 - - - - D20 C22 C18 C19 D17 C21 - - - - - - B16 ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number A15 D12 A14 B13 - - - - A13 B12 C13 A12 C12 A11 - - - - - - D11 B11 E12 C11 F12 B10 - - ...
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Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - - - ispMACH 5000B Family Data Sheet Bank Number - ...
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Lattice Semiconductor Part Number Description Device Family Device Number 5128 = 128 Macrocells 5256 = 256 Macrocells 5384 = 384 Macrocells 5512 = 512 Macrocells Supply Voltage B = 2.5V Speed 3 = 3.0ns 4 = 4.0ns 45 = 4.5ns ...
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Lattice Semiconductor Device Part Number LC5512B-45Q208C LC5512B-45F256C LC5512B-45F484C LC5512B-75Q208C LC5512B LC5512B-75F256C LC5512B-75F484C LC5512B-10Q208C LC5512B-10F256C LC5512B-10F484C Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial grade -5xxxxI. The ...
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Lattice Semiconductor For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 5000B family: • sysIO Design and Usage Guidelines (TN1000) • Power Estimation in ispMACH 5000B Devices (TN1023) ...