lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet - Page 2

• Manufacturer Part Number: lc51024vg
• Description: 3.3v In-system Programmable Superbig, Superwide High Density Plds Tm Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 1. Functional Block Diagram
The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form groups of five
product term clusters, which feed the product term sharing array and the macrocell directly. The ispMACH 5000B allows
up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is
designed to provide flexible clocking and control functionality with the capability to select between global, product
term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if
required, the sysIO cell.
All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate
I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging
interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage
requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing stan-
dards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide
range of standards allows designers to achieve significantly higher board-level performance compared to the more
traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices.
ispMACH 5000B Architecture
The ispMACH 5000B Family of In-System Programmable (ISP™) high density programmable logic devices is
based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to
drive any or all of the GLBs. This mechanism allows fast, efficient connections across the entire device. Figure 1
shows the basic ispMACH 5000B architecture.
Generic Logic Block
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms
and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true
VCCO0
VCCO1
GCLK0
VREF0
VREF1
GCLK1
TOE
I/O Bank 0
I/O Bank 1
Generic
Generic
Logic
Block
Logic
Block
2
ispMACH 5000B Family Data Sheet
I/O Bank 3
I/O Bank 2
Generic
Generic
Block
Block
Logic
Logic
VCCO3
VREF3
GCLK3
TDI
TDO
TMS
TCK
GCLK2
VCCO2
VREF2
RESETB
GOE1
GOE2