SI2107 SILABS [Silicon Laboratories], SI2107 Datasheet - Page 21

• Manufacturer Part Number: SI2107
• Description: SATELLITE RECEIVER FOR DVB-S/DSS
• Manufacturer: SILABS [Silicon Laboratories]

The interrupt signal polarity can be configured to be
active high or active low using the interrupt polarity bit,
INTP. The interrupt signal type can be configured to be
CMOS output or open-drain/source output using the
interrupt type bit, INTT.
Receiver lock
Receiver unlock
Tuner lock
AGC lock
AGC threshold
Carrier estimation lock
Symbol rate estimation lock
Symbol timing lock
Symbol timing unlock
Carrier recovery lock
Carrier recovery unlock
Viterbi lock
Viterbi unlock
Frame synchronizer lock
Frame synchronizer unlock
Acquisition fail
C/N measurement complete
Viterbi BER measurement complete
RS measurement complete
Message FIFO empty
Message FIFO full
Message received
Message parity error
Message receive timeout
Short-circuit detect
Overcurrent detect
Event
Table 16. Events, Interrupts, and Status Bits
Preliminary Rev. 0.7
Interrupt Bit
MSGTO_I
AGCTS_I
MSGPE_
MSGR_I
RCVU_I
RSER_I
RCVL_I
AGCL_I
VTBR_I
TUNL_I
CRU_I
OCD_I
AQF_I
SCD_I
CEL_I
SRL_I
STU_I
CRL_I
VTU_I
FSU_I
STL_I
VTL_I
FSL_I
CN_I
FE_I
FF_I
Interrupt bits are set by the device to 1 when an
interrupt occurs. The host clears an interrupt bit by
writing a 1 again, at which time the device resets the
interrupt bit to zero. Table 16 illustrates the interrupt
sources and their associated status, enable, and
interrupt bits.
Enable Bit
MSGPE_E
MSGTO_E
AGCTS_E
RCVU_E
AGCL_E
RSER_E
RCVL_E
TUNL_E
VTBR_E
MSGR_
OCD_E
CRU_E
SCD_E
CEL_E
SRL_E
STU_E
CRL_E
VTU_E
FSU_E
AQF_E
STL_E
VTL_E
FSL_E
CN_E
FE_E
FF_E
Si2107/08/09/10
MSGPE (0 –> 1)
MSGTO (0 –> 1)
AGCTS (0 –> 1)
RSERS (1 –> 0)
VTBRS (1 –> 0)
MSGR (0 –> 1)
RCVL (1 –> 0)
AGCL (0 –> 1)
TUNL (0 –> 1)
RCVL (0 –>1)
OCD (0 –> 1)
AQF (0 –> 1)
CNS (1 –> 0)
SCD (0 –> 1)
CEL (0 –> 1)
SRL (0 –> 1)
CRL (0 –> 1)
CRL (1 –> 0)
STL (0 –> 1)
STL (1 –> 0)
VTL (0 –> 1)
VTL (1 –> 0)
FSL (0 –> 1)
FSL (1 –> 0)
FE (0 –> 1)
FF (0 –> 1)
Status Bit
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