SI2107 SILABS [Silicon Laboratories], SI2107 Datasheet - Page 20

• Manufacturer Part Number: SI2107
• Description: SATELLITE RECEIVER FOR DVB-S/DSS
• Manufacturer: SILABS [Silicon Laboratories]

Si2107/08/09/10
The device has one output pin (pin 30), which can be
configured as either a receiver lock indicator, general
purpose output, or interrupt output, using the pin select
register, PSEL. The receiver lock indicator provides a
signal output for register bit RCVL. The general purpose
output reflects the polarity of register bit GPO. The
interrupt output is discussed further in “6.2. Interrupts”.
The user can configure the device such that
components of the channel decoder are bypassed. This
is controlled by the energy-dispersal descrambler
bypass bit, DS_BP, the Reed-Solomon decoder bypass
bit, RS_BP, and the convolutional de-interleaver bypass
bit, DI_BP. The use of these bypass options is defined
for the implementation of a BER test on a known
modulated PRBS data sequence as explained later in
"6.5. Channel Decoder" on page 24.
20
TS_SYNC active high
TS_SYNC, active low/1-bit wide
TS_CLK, rising edge
TS_ERR active high
TS_VAL active high
TS_CLK falling edge/ gapped
Parallel Data Mode
TS_DATA[7:0]
TS_SYNC active high
TS_CLK rising edge
TS_ERR active high
TS_ERR, active low
TS_VAL active high
TS_VAL active low
Continuous Serial Data Mode
Gapped Serial Data Mode
TS_DATA[0]
TS_DATA[0]
TS1 (sync)
TS1 (sync)
TS1 (sync)
Figure 7. MPEG-TS Parallel Mode
Figure 8. MPEG-TS Serial Modes
TS2
TS2
TS2
Preliminary Rev. 0.7
6.2. Interrupts
The device is equipped with several sticky interrupt bits
to provide precise event tracking and monitoring.
Next to interrupts being signaled via the I2C register
map, the user can program one of the device terminals
(INT) as a dedicated interrupt pin via the pin select
register bit, PSEL. The device contains an extensive
collection of interrupt sources that can be individually
masked from the INT pin using the corresponding
interrupt enable register bits, labeled with suffix “_E”.
Thus, the INT output is a logical-OR of all enabled
interrupts. Generation of the channel interrupt on pin
INT can be masked off by using the interrupt enable bit,
INT_EN. Note that interrupt reporting in the register
map is not affected by INT_EN.
TS188
TS188
TS188
RS1
RS1
RS1
TS1 (sync)
TS1 (sync)
TS1 (sync)
TS2
TS2
TS2