A40MX02-1BG100 ACTEL [Actel Corporation], A40MX02-1BG100 Datasheet - Page 44
A40MX02-1BG100
Manufacturer Part Number
A40MX02-1BG100
Description
40MX and 42MX FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A40MX02-1BG100.pdf
(123 pages)
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Table 28 •
1 -3 8
Parameter Description
TTL Output Module Timing
t
t
t
t
t
t
d
d
CMOS Output Module Timing
t
t
t
t
t
t
d
d
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
4. Delays based on 35pF loading.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
TLH
THL
TLH
THL
40MX and 42MX FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to
HIGH
Enable Pad Z to
LOW
Enable Pad HIGH to
Z
Enable Pad LOW to
Z
Delta LOW to HIGH
Delta HIGH to LOW
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to
HIGH
Enable Pad Z to
LOW
Enable Pad HIGH to
Z
Enable Pad LOW to
Z
Delta LOW to HIGH
Delta HIGH to LOW
4
4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
CC
0.02
0.03
0.03
0.02
3.3
4.0
3.9
3.4
3.7
4.7
7.9
5.9
3.4
4.9
7.9
5.9
= 4.75V, T
v6.0
‘–2’ Speed
J
= 70°C)
0.02
0.03
0.04
0.02
3.8
4.6
4.3
5.4
9.1
6.8
4.5
3.9
3.9
5.6
9.1
6.8
‘–1’ Speed
10.4
0.03
0.03
10.4
0.04
0.03
4.3
5.2
4.9
6.1
7.7
5.1
4.4
4.4
6.4
7.7
‘Std’ Speed
12.2
0.03
0.04
6.05
12.2
0.05
0.03
5.1
6.1
5.8
7.2
9.0
5.2
5.2
7.5
9.0
‘–F’ Speed
7.2
8.6
8.0
10.1
17.1
12.6
0.04
0.06
8.5
7.3
7.3
10.5
17.0
12.6
0.07
0.04
Units
ns/pF
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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