A40MX02-1BG100 ACTEL [Actel Corporation], A40MX02-1BG100 Datasheet - Page 26

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A40MX02-1BG100

Manufacturer Part Number
A40MX02-1BG100
Description
40MX and 42MX FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Output Drive Characteristics for 3.3V PCI Signaling
Table 19 •
Table 20 •
1 -2 0
Symbol
V
V
V
I
I
V
V
C
C
L
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for V
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Symbol
I
Slew (r)
Slew (f)
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
IH
IL
CL
PIN
CCI
IH
IL
OH
OL
40MX and 42MX FPGA Families
IN
CLK
DC Specification (3.3V PCI Signaling)
AC Specifications for (3.3V PCI Signaling)*
Input High Leakage Current
Output Rise Slew Rate
Output Fall Slew Rate
Low Clamp Current
Supply Voltage for I/Os
Input Leakage Current
Input Pin Capacitance
Output High Voltage
CLK Pin Capacitance
Output Low Voltage
Input High Voltage
Input Low Voltage
Parameter
Pin Inductance
Parameter
CCI
–0.5V to 7.0V.
0.2V to 0.6V load
0.6V to 0.2V load
–5 < V
Condition
I
I
OUT
Condition
OUT
V
IN
6 mA
= –2 mA
= 3 mA,
IN
= 2.7V
1
–1
v6.0
–25 + (V
Min.
–0.5
0.5
0.9
3.0
5
/0.015
Min.
1
1
PCI
IN
+1)
PCI
V
CC
Max.
–70
3.6
0.8
0.1
12
70
10
20
+ 0.5
Max.
4
4
Min.
–0.3
3.0
0.5
3.3
Min.
–60
1.8
2.8
MX
V
MX
0.1 V
< 8 nH
CCI
Max.
–10
3.6
0.8
10
10
10
+ 0.3
CCI
Max.
–10
3
2.8
4.0
Units
µA
µA
nH
pF
pF
Units
V
V
V
V
V
V/ns
V/ns
mA

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