A40MX02-1BG100 ACTEL [Actel Corporation], A40MX02-1BG100 Datasheet - Page 34

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A40MX02-1BG100

Manufacturer Part Number
A40MX02-1BG100
Description
40MX and 42MX FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Decode Module Timing
Figure 1-28 • Decode Module Timing
SRAM Timing Characteristics
Figure 1-29 • SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
Note: Identical timing for falling edge clock.
Figure 1-30 • 42MX SRAM Write Operation
1 -2 8
40MX and 42MX FPGA Families
A–G, H
WRAD[5:0]
Y
C
D
G
A
B
E
F
WD[7:0]
BLKEN
WCLK
WRAD [5:0]
BLKEN
WEN
WCLK
WD [7:0]
WEN
Write Port
t PLH
50%
H
t
t
t
Valid
Valid
ADSU
WENSU
BENSU
3 2x8 or 64x4
RAM Array
(2 56 Bits)
v6.0
t
RCKHL
t
t
t
ADH
BENH
WENH
t PHL
t
Read Port
RDAD [5:0]
RCKHL
RD [7:0]
RCLK
Y
LEW
REN

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