w3e16m72s-xbx White Electronic Designs Corporation, w3e16m72s-xbx Datasheet - Page 6

• Manufacturer Part Number: w3e16m72s-xbx
• Description: 16mx72 Sdram
• Manufacturer: White Electronic Designs Corporation

February 2005
Rev. 7
FIGURE 3 – MODE REGISTER DEFINITION
0*
* M14 and M13
BA
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
1
0*
BA
0
M12
0
0
-
A
12
Operating Mode
A
M11
0
0
-
11
White Electronic Designs
A
10
M10
0
0
-
A
9
M9
A
0
0
-
8
A
7
M8
CAS Latency
0
1
-
A
6
M7
A
0
0
-
5
A
BT
4
M3
0
1
M6-M0
Valid
Valid
A
-
3
M2
M6
Burst Length
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
M1
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
M0
M4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
A
1
A
Reserved
Reserved
Reserved
Reserved
Reserved
0
M3 = 0
Interleaved
Burst Type
Sequential
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2.5
2
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8
6
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
4. Whenever a boundary of the block is reached within a given sequence above, the
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength, and
QFC#. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. The enabling of the DLL should always be followed
by a LOAD MODE REGISTER command to the mode
register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller
must wait the specifi ed time before initiating any subsequent
operation. Violating either of these requirements could
result in unspecifi ed operation.
Length
Burst
column within the block.
starting column within the block.
starting column within the block.
following access wraps within the block.
2
4
8
White Electronic Designs Corporation • [phone] • www.wedc.com
Starting Column
A2
0
0
0
0
1
1
1
1
TABLE 1 – BURST DEFINITION
Address
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
Type = Sequential
W3E16M72S-XBX
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Type = In ter leaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0