w3e16m72s-xbx White Electronic Designs Corporation, w3e16m72s-xbx Datasheet

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w3e16m72s-xbx

Manufacturer Part Number
w3e16m72s-xbx
Description
16mx72 Sdram
Manufacturer
White Electronic Designs Corporation
Datasheet
16Mx72 DDR SDRAM
FEATURES
* This product is subject to change without notice..
February 2005
Rev. 7
DDR SDRAM Rate = 200, 250, 266
Package:
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 72
Weight: W3E16M72S-XBX – 3.55 grams typical
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
Count
Area
White Electronic Designs
I/O
22.3
TSOP
11.9
66
Monolithic Solution
5 x 66 pins = 330 pins
5 x 265mm 2 = 1328mm 2
TSOP
11.9
66
TSOP
11.9
66
11.9
1
BENEFITS
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally confi gured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
TSOP
11.9
66
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density
(W3E32M72S-XBX)
• 34% I/O Reduction
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3E16M72S-XBX
Actual Size
W3E16M72S-XBX
219 Balls
800mm 2
32
W3E16M72S-XBX
25
40%
34%
N
G
S
A
V
S
I

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w3e16m72s-xbx Summary of contents

Page 1

... Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military Temperature Ranges Organized as 16M x 72 Weight: W3E16M72S-XBX – 3.55 grams typical * This product is subject to change without notice.. Monolithic Solution 11.9 66 22.3 TSOP ...

Page 2

... DQ72 DQ71 DQ70 V V DQ75 DQ74 DQ69 DQ68 DQ77 DQ76 DQ67 DQ66 DQ79 DQ78 DQ65 DQ64 CCQ CCQ 2 W3E16M72S-XBX V V DQ16 DQ17 DQ31 V CCQ CCQ DQ18 DQ19 DQ29 DQ30 DQ20 DQ21 DQ27 DQ28 ...

Page 3

... CLK CLK # CLK CKE CKE CS DQML DQML DQMH DQMH 4 DQSL DQSL 4 DQSH DQSH 4 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX # ...

Page 4

... The address bits registered coincident with the READ or WRITE command are used to select the February 2005 Rev. 7 W3E16M72S-XBX starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register defi ...

Page 5

... The programmed burst length applies to both READ and WRITE bursts. February 2005 Rev. 7 W3E16M72S-XBX BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. ...

Page 6

... Violating either of these requirements could result in unspecifi ed operation. 6 W3E16M72S-XBX TABLE 1 – BURST DEFINITION Order of Accesses Within a Burst Starting Column Address ...

Page 7

... ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided 7 W3E16M72S-XBX FIGURE 5 – EXTENDED MODE REGISTER DEFINITION ...

Page 8

... The bank(s) will be available for a subsequent row access a specifi ed time (t issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX RAS# CAS# WE ...

Page 9

... A simple algorithm for meeting both refresh and DLL re- quirements is to apply NOPs for 200 clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only. 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX between AC later. , because XSNR ...

Page 10

... Input Capacitance: All other input-only pins -40 to +85 °C Input/Output Capacitance: I/Os -55 to +150 °C Symbol Max Units Notes 13.7 ° C/W 1 10.3 ° C/W 1 3.9 ° 1 C/W 10 W3E16M72S-XBX CAPACITANCE (NOTE 13) Symbol C I1 Input Capacitance CA 0 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Max Unit ...

Page 11

... CKE = LOW (23, 32, 50 (MAX RAS REF 7.8125µs (27, 50) REF Standard (11) =t (MIN White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX Symbol Min Max V 2.3 2 2.3 2.7 CCQ - ...

Page 12

... WTR DQSQ t 70.3 REFC t 35 REFC t 7.8 REFI t 3.9 REFI t 0 VTD t 75 XSNR t 200 XSRD 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX 250Mbps CL2.5 200Mbps CL2.5 200Mbps CL2 150Mbps CL2 Min Max Min Max Units -0.8 +0.8 -0.8 +0.8 ns 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. ...

Page 13

... Minimum -140 -160 -180 -200 2.0 2.5 0.0 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX stabilizes. Exception: during the period REF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW transitions occur in the same access time windows as valid data DQSS for I measurements is the smallest multiple of t ...

Page 14

... Nominal low -50 Minimum -60 -70 -80 0.0 2.0 2.5 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX level and the referenced CC +1.5V for a pulse width ≤ 3ns and the pulse width CCQ (MAX) HZ (MAX) will prevail over t (MAX (MAX) condition. DQSCK RPST (MIN (MAX) condition ...

Page 15

... NOM 1.27 (0.050) NOM ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES February 2005 Rev. 7 Bottom View 32.1 (1.264) MAX 219 X Ø 0.762 (0.030) NOM 19.05 (0.750) NOM 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX 25.1 J (0.988) H MAX ...

Page 16

... PACKAGE 219 Plastic Ball Grid Array (PBGA) DEVICE GRADE Military -55°C to +125° Industrial -40°C to +85° Commercial 0°C to +70°C February 2005 Rev. 7 ORDERING INFORMATION W 3E 16M XXX White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX ...

Page 17

... Rev 7 Changes (Pg. 1, 11, 17) 7.1 Update I Specifi cations table CC February 2005 Rev pg White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M72S-XBX Release Date Status April 2002 Advanced September 2002 Advanced November 2002 Preliminary December 2002 Preliminary November 2003 ...

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