w3e16m72s-xbx White Electronic Designs Corporation, w3e16m72s-xbx Datasheet - Page 4

• Manufacturer Part Number: w3e16m72s-xbx
• Description: 16mx72 Sdram
• Manufacturer: White Electronic Designs Corporation

along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered
at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst
access.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
February 2005
Rev. 7
White Electronic Designs
4
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register defi nition, command
descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefi ned manner. Operational procedures other than
those specifi ed may result in undefi ned operation. Power
must fi rst be applied to V
then to V
after V
permanent damage to the device. V
time after V
with V
valid until after V
but will detect an LVCMOS LOW level after V
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply
and reference voltages are stable, and the clock is stable,
the DDR SDRAM requires a 200µs delay prior to applying
an executable command.
Once the 200µs delay has been satisfi ed, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required. Following
these requirements, the DDR SDRAM is ready for normal
operation.
TT
CCQ
White Electronic Designs Corporation • [phone] • www.wedc.com
. Except for CKE, inputs are not recognized as
REF
CCQ
to avoid device latch-up, which may cause
(and to the system V
RFC
but is expected to be nominally coincident
REF
must be satisfi ed.) Additionally, a LOAD
is applied. CKE is an SSTL_2 input
CC
W3E16M72S-XBX
and V
CCQ
TT
REF
). V
simultaneously, and
TT
can be applied any
must be applied
CC
is applied.