w3e16m64s-xbx White Electronic Designs Corporation, w3e16m64s-xbx Datasheet - Page 7

• Manufacturer Part Number: w3e16m64s-xbx
• Description: 16mx64 Sdram
• Manufacturer: White Electronic Designs Corporation

OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specifi ed to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automatically.)
Any time the DLL is enabled, 200 clock cycles must occur
before a READ command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
February 2005
Rev. 4
COMMAND
COMMAND
DQS
DQS
CLK#
CLK
DQ
CLK#
CLK
DQ
FIGURE 4 – CAS LATENCY
DATA
White Electronic Designs
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t
T0
T0
TRANSITIONING DATA
CL = 2
NOP
NOP
CL = 2.5
T1
T1
AC
and nominal t
NOP
NOP
T2
T2
T2n
DSDQ
T2n
DON'T CARE
NOP
NOP
T3
T3
T3n
T3n
7
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until t
FIGURE 5 – EXTENDED MODE REGISTER
0 1
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
BA
E12
0
-
1
1 1
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E11
BA
0
-
0
E10
0
A
-
12
E9
0
A
-
11
E8
0
-
A
10
E7
0
-
Operating Mode
A
9
E6
0
-
DEFINITION
A
8
E5
0
-
A
E4
7
0
-
W3E16M64S-XBX
A
E3
0
6
-
A
E2
0
-
5
A
4
E1, E0
Valid
MRD
A
-
3
A
DS
2
is met.
E1
0
1
A
1
DLL
E0
Operating Mode
A
0
1
0
Reserved
Reserved
Drive Strength
Extended Mode
Register (Ex)
Reduced
Address Bus
Normal
Disable
Enable
DLL