w3e16m64s-xbx White Electronic Designs Corporation, w3e16m64s-xbx Datasheet

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w3e16m64s-xbx

Manufacturer Part Number
w3e16m64s-xbx
Description
16mx64 Sdram
Manufacturer
White Electronic Designs Corporation
Datasheet
16Mx64 DDR SDRAM
FEATURES
* This product is subject to change without notice.
February 2005
Rev. 4
DDR Data Rate = 200, 250, 266Mbps
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 64
Weight: W3E16M64S-XBX - 2 grams typical
White Electronic Designs
Count
Area
I/O
22.3
TSOP
11.9
66
4 x 265mm 2 = 1060mm 2
Monolithic Solution
4 x 66 pins = 264 pins
TSOP
66
TSOP
11.9
66
TSOP
66
TSOP
11.9
66
TSOP
66
1
BENEFITS
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally confi gured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
TSOP
11.9
TSOP
66
66
50% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 17% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density
(W3E32M64S-XBX)
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3E16M64S-XBX
White Electronic Designs
W3E16M64S-XBX
Actual Size
219 Balls
525mm 2
25
W3E16M64S-XBX
21
50%
17%
G
S
A
V
N
S
I

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w3e16m64s-xbx Summary of contents

Page 1

... Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military Temperature Ranges Organized as 16M x 64 Weight: W3E16M64S-XBX - 2 grams typical * This product is subject to change without notice. 11.9 66 22.3 TSOP Area ...

Page 2

... DQ55 DQ58 CCQ CCQ 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX V V DQ25 DQ27 DQ29 V CCQ CCQ DQ22 DQ20 DQ18 DQ31 DQ24 DQ26 DQ28 DQ16 SS SS ...

Page 3

... Y CLK # CLK CKE CKE CS DQML DQML 3 DQ DQMH DQMH 3 DQSL DQSL 3 DQSH DQSH 3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX RAS # 0 CAS # RAS # 1 CAS ...

Page 4

... READ or WRITE command are used to select the starting column location for the burst access. February 2005 Rev. 4 W3E16M64S-XBX Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register defi nition, command descriptions and device operation. ...

Page 5

... The programmed burst length applies to both READ and WRITE bursts. February 2005 Rev. 4 W3E16M64S-XBX BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. ...

Page 6

... Violating either of these requirements could result in unspecifi ed operation. 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX TABLE 1 – BURST DEFINITION Order of Accesses Within a Burst Starting Column Address ...

Page 7

... Operations already in progress are not affected. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t 7 W3E16M64S-XBX DEFINITION ...

Page 8

... The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specifi ed time (t 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX RAS# CAS# WE ...

Page 9

... A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only. 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX between updates. AC later. , because XSNR ...

Page 10

... Input Capacitance: All other input-only pins -40 to +85 °C Input/Output Capacitance: I/Os -55 to +150 °C Max Units Notes 14.5 °C/W 1 10.0 °C/W 1 5.4 °C White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX CAPACITANCE (NOTE 13) Symbol Max CI1 CI2 8 CIO 12 Unit ...

Page 11

... CKE = HIGH; Address and other control CK CK for DQ, DQS, and DM (51 RAS = 0mA (22, 48) OUT 7.8125µs (27, 50 (MIN White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX (NOTES 1, 6) Symbol Min Max V 2.3 2 2.3 2.7 CCQ 0. 0.04 IH REF REF V -0 ...

Page 12

... WTR DQSQ t 70.3 REFC t 7.8 REFI t 0 VTD t 75 XSNR t 200 XSRD 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX 250 Mbps CL2.5 200 Mbps CL2.5 200 Mbps CL2 150 Mbps CL2 Min Max Min Max Units -0.8 +0.8 -0.8 +0.8 ns 0.45 0.55 0.45 0. 0.45 0.55 0.45 0.55 ...

Page 13

... This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (t standby). FIGURE B – PULL-UP CHARACTERISTICS Maximum Nominal high Nominal low Minimum 2.0 2.5 13 W3E16M64S-XBX . REF stabilizes. Exception: during the period REF stabilizes, CKE ≤ 0 recognized as LOW. REF CCQ . TT ...

Page 14

... FIGURE D – PULL-UP CHARACTERISTICS Maximum Nominal high Nominal low Minimum 2.0 2.5 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX level and the referenced CC (MAX +1.5V for a pulse width ≤ 3ns and the pulse width IH CCQ must track each other. (MAX) will prevail over t (MAX (MAX) condition ...

Page 15

... ∅ 219 x 0.762 (0.030) NOM 19.05 (0.750) NOM ORDERING INFORMATION 16M XXX B X -55°C to +125°C -40°C to +85°C 0°C to +70°C 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3E16M64S-XBX 21.1 (0.831) MAX 0.61 (0.024) NOM 2.03 (0.080) MAX ...

Page 16

... Changes (Pg. 1, 11, 16) 4.1 Changes 12mA minimum OH OL 4.2 Update I Specifi cations table values CC February 2005 Rev. 4 W3E16M64S-XBX Release Date Status December 2002 May 2003 November 2003 September 2004 February 2005 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Advanced Advanced ...

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