w3e16m64s-xbx White Electronic Designs Corporation, w3e16m64s-xbx Datasheet - Page 13

• Manufacturer Part Number: w3e16m64s-xbx
• Description: 16mx64 Sdram
• Manufacturer: White Electronic Designs Corporation

NOTES:
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard
6. V
7. V
8. V
9. The value of V
10. I
11. Enables on-chip refresh and address counters.
12. I
13. This parameter is not tested but guaranteed by design. t
14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates 1V/ns
February 2005
Rev. 4
FIGURE A – PULL-DOWN CHARACTERISTICS
at nominal reference/supply voltage levels, but the related specifi cations and device
operation are guaranteed for the full voltage range specifi ed.
environment, but input timing is still referenced to V
CLK/CLK#), and parameter specifi cations are guaranteed for the specifi ed AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between V
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
the DC level of the same. Peak-to-peak noise (noncommon mode) on V
exceed ±2 percent of the DC value. Thus, from V
DC error and an additional ±25mV for AC noise. This measurement is to be taken
at the nearest V
resistors, is expected to be set equal to V
level of V
level on CLK#.
and must track variations in the DC level of the same.
with minimum cycle time with the outputs open.
at the defi ned cycle rate.
and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns,
CC
CC
REF
TT
ID
is dependent on output loading and cycle rates. Specifi ed values are obtained
specifi cations are tested after the device is properly initialized, and is averaged
is the magnitude of the difference between the input level on CLK and the input
is not applied directly to the device. V
is expected to equal V
REF
.
160
140
120
100
80
60
40
20
IX
0
CC
REF
0.0
and V
tests may use a V
White Electronic Designs
by-pass capacitor.
CC
MP
, and electrical AC and DC characteristics may be conducted
are expected to equal V
0.5
Output
(V
SS
CCQ/2
OUT
.
)
of the transmitting device and to track variations in
IL
1.0
V
-to-V
V
TT
OUT
50Ω
30pF
TT
REF
Reference
Point
IH
(V)
is a system supply for signal termination
swing of up to 1.5V in the test
and must track variations in the DC
1.5
CCQ/2
CCQ/2
REF
, V
of the transmitting device
(or to the crossing point for
IL
A
(AC) and V
REF
2.0
= 25°C, f = 1 MHz
Nominal high
Nominal low
is allowed ±25mV for
Maximum
Minimum
IH
2.5
(AC).
REF
may not
13
15. The CLK/CLK# input reference level (for timing referenced to CLK/CLK#) is the
16. Inputs are not recognized as valid until V
17. The output timing reference level, as measured at the timing reference point
18. t
19. The maximum limit for this parameter is not a device limit. The device will operate
20. This is not a device limit. The device will operate with a negative value, but system
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
22. MIN (t
23. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
25. The valid data window is derived by achieving other specifi cations - t
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8-
27. This limit is actually a nominal value and does not result in a fail value. CKE is
timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
point at which CLK and CLK# cross; the input reference level for signals other than
CLK/CLK# is V
before V
indicated in Note 3, is V
transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
with a greater value for this parameter, but system performance (bus turnaround)
will degrade accordingly.
performance could be degraded due to bus turnaround.
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t
the minimum absolute value for the respective parameter. t
measurements is the largest multiple of t
for t
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
maximum amount for any given device.
t
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
DQ15 of each chip.
HIGH during REFRESH command period (t
standby).
FIGURE B – PULL-UP CHARACTERISTICS
HZ
DQSQ
and t
RAS
, and t
RC
.
White Electronic Designs Corporation • [phone] • www.wedc.com
REF
LZ
or t
transitions occur in the same access time windows as valid data
QH
stabilizes, CKE ≤ 0.3 x V
RFC
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
(t
0
REF
) for I
QH
0.0
.
= t
CC
HP
TT
measurements is the smallest multiple of t
- t
.
QHS
0.5
). The data valid window derates directly porportional
W3E16M64S-XBX
V
1.0
CCQ
CCQ -
CK
REF
V
is recognized as LOW.
OUT
that meets the maximum absolute value
RFC
stabilizes. Exception: during the period
(V)
1.5
[MIN]) else CKE is LOW (i.e., during
2.0
RAS
Nominal high
Nominal low
Minimum
Maximum
DQSS
(MAX) for I
CK
.
HP
that meets
2.5
(t
CK/2
CC
),