w3e16m64s-xbx White Electronic Designs Corporation, w3e16m64s-xbx Datasheet - Page 14

• Manufacturer Part Number: w3e16m64s-xbx
• Description: 16mx64 Sdram
• Manufacturer: White Electronic Designs Corporation

28. To maintain a valid level, the transitioning edge of the input must:
29. The Input capacitance per pin group will not differ by more than this maximum
30. CLK and CLK# input slew rate must be ≥ 1V/ns (≥2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
32. V
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
34. t
35. READs and WRITEs with auto precharge are not allowed to be issued until
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
37. Normal Output Drive Curves:
38. Reduced Output Drive Curves:
February 2005
Rev. 4
FIGURE C – PULL-DOWN CHARACTERISTICS
amount for any given device.
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to t
4V/ns, functionality is uncertain.
by the same amount.
CLK and CLK# inputs, collectively during bank active.
t
2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive.
HP
RAS
a) Sustain a constant slew rate from the current AC level through to the target AC
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
CC
a) The full variation in driver pull-down current from minimum to maximum
b) The variation in driver pull-down current within nominal limits of voltage and
c) The full variation in driver pull-up current from minimum to maximum process,
d) The variation in driver pull-up current within nominal limits of voltage and
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
f) The full variation in the ratio of the nominal pull-up to pull-down current should
a) The full variation in driver pull-down current from minimum to maximum
min is the lesser of t
(MIN) can be satisfi ed prior to the internal precharge command being issued.
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
level, V
must not vary more than 4% if CKE is not active while any bank is active.
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
current should be between .71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0 Volt, and at the same voltage and temperature.
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure C.
level, V
DS
IL
IL
and t
(DC) or V
(AC) or V
80
70
60
50
40
30
20
10
0
DH
0.0
White Electronic Designs
for each 100mV/ns reduction in slew rate. If slew rate exceeds
IH
IH
CL
(DC).
(AC).
minimum and t
0.5
1.0
V
OUT
CH
(V)
minimum actually applied to the device
1.5
2.0
Nominal high
Nominal low
Maximum
Minimum
2.5
14
39. The voltage levels used are derived from a minimum V
40. V
41. V
42. This maximum value is derived from the referenced test load. In practice, the values
43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.
44. During initialization, V
45. The current part operates below the slowest JEDEC operating frequency of 83
46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is executed.
51. I
52. Whenever the operating frequency is altered, not including jitter, the DLL is required
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signifi cantly different voltage values.
can not be greater than 1/3 of the cycle rate.
obtained in a typical terminated design may refl ect up to 310ps less for t
and the last DVW. t
t
Alternatively, V
volts, provided a minimum of 42 ohms of series resistance is used between the V
supply and the input pin.
MHz. As such, future die may not refl ect this option.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t
I
remain stable. Although I
to be reset. This is followed by 200 clock cycles before any READ command.
FIGURE D – PULL-UP CHARACTERISTICS
LZ
CC2N
CC2Q
b) The variation in driver pull-down current within nominal limits of voltage and
c) The full variation in driver pull-up current from minimum to maximum process,
d) The variation in driver pull-up current within nominal limits of voltage and
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
f) The full variation in the ratio of the nominal pull-up to pull-down current should
IH
CC
(MIN) will prevail over t
overshoot: V
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.
and V
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure D.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure C.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
current should be between .71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0 V, and at the same voltage and temperature.
specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.
is similar to I
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CCQ
must track each other.
TT
-10
-20
-30
-40
-50
-60
-70
-80
IH
0
may be 1.35V maximum during power up, even if V
(MAX) = V
CC2F
0.0
HZ
(MAX) will prevail over t
CCQ
except I
CC2F
, V
DQSCK
0.5
TT
CCQ
, I
, and V
CC2N
CC2Q
(MIN) + t
+1.5V for a pulse width ≤ 3ns and the pulse width
, and I
W3E16M64S-XBX
specifi es the address and control inputs to
V
REF
1.0
CCQ -
RFC
RPRE
must be equal to or less than V
V
CC2Q
OUT
has been satisfi ed.
(MAX) condition.
(V)
DQSCK
are similar, I
1.5
(MAX) + t
CC
2.0
Nominal high
level and the referenced
Nominal low
CC2F
Maximum
Minimum
RPST
is “worst case.”
(MAX) condition.
2.5
CC
/V
HZ
CC
CCQ
(MAX)
+ 0.3V.
are 0
TT