cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 171
cx28348
Manufacturer Part Number
cx28348
Description
Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28348.pdf
(195 pages)
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CX28342/3/4/6/8 Data Sheet
Table 4-9. Motorola Asynchronous Read Cycle (MOTO* = 0)
Figure 4-10. Motorola Asynchronous Write Cycle (MOTO* = 0)
28348-DSH-001-B
FOOTNOTE:
(1)
(2)
Symbol
DTACK*
Clk is the cycle (ns) of the slowest clock (DS3—22 ns, E3—29 ns).
The transition must be completed, i.e., DS* must rise after DTACK* low.
AD[7:0]
A[8:0]
1
2
3
4
5
6
7
8
9
R/W*
CS*
DS*
A[8:0] Address setup to DS* low
A[8:0] Address hold after DS* high
R/W* high & CS* low to DS* low
DS* high to CS* high and R/W* invalid
DTACK* low to AD[7:0] valid
DS* low to DTACK* low
DS* high to AD[7:0] invalid or three-state
DS* high to next DS* low
DS* high to DTACK* highZ
Parameter
Address
Mindspeed Technologies™
1
3
5
Minimum
Write Data
8
—
—
—
15
—
4
3
3
3
6
Electrical and Mechanical Specifications
3 x clk + 15
Maximum
—
—
—
—
13
13
—
19
9
4
4
2
7
(1)
Units
100542_031
ns
ns
ns
—
ns
ns
ns
ns
ns
4
-
11
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