cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 144

• Manufacturer Part Number: cx28348
• Description: Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
• Manufacturer: Mindspeed Technologies

Registers
Value after reset: 00(h)
Direction: Read only
Value after enable: Unaffected (affected indirectly by other registers)
TxDLFEACItr
RxDLltr
RxFEACltrs
AlarmEndItr
AlarmStrtItr
Ctrltr
3-32
Reserved
7
Reserved
Transmit Data Link/FEAC Interrupt Source—Set if one or more of the interrupt-related active
status bits in the Transmit Data Link FEAC Status register are high. Cleared when the bits
related to interrupt activation in the Transmit Data Link FEAC Status register or their interrupt
masks are low.
Receive Data Link Interrupt Source—Set if one or more of the interrupt-related active status
bits in the Receive Data Link Status register are high. Cleared when the bits related to interrupt
activation in the Receive Data Link Status register or their interrupt masks are low.
Receive FEAC Interrupt Source—Set if one or more of the interrupt related active status bits
in the Receive FEAC Status register are high. Cleared when the bits related to interrupt
activation in the Receive FEAC Status register or their interrupt masks are low.
Alarm End Interrupt Source—Set if one or more of the active status bits in the Alarm End
Interrupt Status register are high. Cleared when the bits related to interrupt activation in the
Alarm End Interrupt Status register or their interrupt masks are low.
Alarm Start Interrupt Source—Set if one or more of the active status bits in the Alarm Start
Interrupt Status register are high. Cleared when the bits related to interrupt activation in the
Alarm Start Interrupt Status register or their interrupt masks are low.
Counter Interrupt Source—Set if one or more of the active status bits in the Counter Interrupt
Status register are high. Cleared when the bits related to interrupt activation in the Counter
Interrupt Status register or their interrupt masks are low.
6
Interrupt Source Status Register (SR01i)
This register identifies which of the other status registers reports the reason for the
interrupt assertion. This register is read at the beginning of the interrupt service
routine, after the source channel was identified.
NOTE:
TxDLFEACItr
5
Mindspeed Technologies™
More than one bit can be high at the same time, due to multiple sources for the
interrupt.
RxDLltr
4
RxFEACltrS
3
AlarmEndItr
2
AlarmStrtItr
CX28342/3/4/6/8 Data Sheet
1
28348-DSH-001-B
Ctrltr
0