cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 120

• Manufacturer Part Number: cx28348
• Description: Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
• Manufacturer: Mindspeed Technologies

Registers
Default after reset: 00(h)
Direction: Read/Write
Modification: Bits 0, 1, 4: dynamic, bits 2, 3: OneSecMod—static
1SecTimIE
OneSecOut
OneSecIn
OneSecMod
SWRst
3-8
Reserved
7
Reserved
One Second Timer Interrupt Enable—A control bit that allows interrupts to appear on the
INTR* pin due to the occurrence of a one-second trigger (see
One-Second Pin Output—When set, defines the ONESEC pin as an output pin, setting the
triggering mode for one-second latching (see
an input or undefined according to the value of the OneSecIn bit in this register. During and
after reset, ONESEC drives high Z (neither in Output State nor in input state).
One-Second Pin Input—When set, defines the ONESEC pin as an input pin, setting the
triggering mode for one-second latching (see
an output or undefined according to the value of OneSecOut bit in this register. During and
after reset, ONESEC drives high Z (neither in output state nor in input state).
One-Second Latching Mode—When set, the one-second latching mode is in effect (see
Section
Software Reset—Setting this bit produces a reset identical to that produced via the RESET*
pin. Internal circuitry clears this bit once the reset is asserted.
6
2.2.6).
General2 Control Register (GCR01)
NOTE:
NOTE:
Reserved
5
Mindspeed Technologies™
OneSecOut and OneSecIn bits should not be both set at the same time.
OneSecOut and OneSecIn bits should not be both set at the same time
1SecTimIE
4
OneSecOut
3
Section
Section
2.2.6). When cleared, ONESEC is either
2.2.6). When cleared, ONESEC is either
OneSecIn
2
Section
OneSecMod
2.2.6)
CX28342/3/4/6/8 Data Sheet
1
28348-DSH-001-B
.
SWRst
0